feat(drivers): HPET high-res timer, LPT parallel port, CMOS NVRAM

Add three real platform device drivers (x86 hardware, ARM-stubbed):

- drivers/timer/hpet.c + include/drivers/hpet.h: High Precision Event Timer.
  Maps the HPET block at the standard 0xFED00000, reads the femtosecond period
  from the capability register, enables the main counter and exposes a
  monotonic nanosecond time source (hpet_get_ns) far finer than the 100 Hz PIT.
- drivers/char/lpt.c + include/drivers/lpt.h: IBM PC parallel port (LPT1) with
  the Centronics data/strobe handshake over ports 0x378/0x379/0x37A.
- drivers/char/nvram.c + include/drivers/nvram.h: MC146818 CMOS NVRAM read/write
  over 0x70/0x71, preserving the NMI-disable bit, with checksum and hex dump.

Wired all three into the [5/14] device-enumeration boot step and added LazyBox
applets `hpet`, `lpt`, and `nvram`.

Verified live under QEMU (screenshotted): HPET reports 100 MHz / 3 comparators /
10 ns period and its counter advances ~1.4 s of real time between two `hpet`
runs; NVRAM dumps 128 bytes with a computed checksum; LPT1 detected at 0x378.
Clean build on x86_64/aarch64/armv8i; 0 panics / 0 OOM.

Co-Authored-By: Claude Opus 4.8 <[email protected]>
Claude-Session: https://claude.ai/code/session_01Fh5z6V7nGPbHvqVG5p4CXX

include/drivers/nvram.h

@@ -0,0 +1,20 @@
+#ifndef _DRIVERS_NVRAM_H
+#define _DRIVERS_NVRAM_H
+
+// CMOS / RTC NVRAM driver. The MC146818-compatible RTC exposes 128 indexed
+// bytes behind ports 0x70 (index) / 0x71 (data); bytes 0x0E..0x7F are the
+// battery-backed scratch RAM used by the BIOS for configuration.
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define NVRAM_SIZE       128
+#define NVRAM_USER_START 0x0E   // first non-RTC (scratch) byte
+
+void    nvram_init(void);
+uint8_t nvram_read(uint8_t index);
+void    nvram_write(uint8_t index, uint8_t value);
+uint8_t nvram_checksum(void);        // simple sum over the scratch region
+void    nvram_dump(void);            // hex dump of all 128 bytes to the console
+
+#endif // _DRIVERS_NVRAM_H