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feat(drivers): HPET high-res timer, LPT parallel port, CMOS NVRAM
Add three real platform device drivers (x86 hardware, ARM-stubbed): - drivers/timer/hpet.c + include/drivers/hpet.h: High Precision Event Timer. Maps the HPET block at the standard 0xFED00000, reads the femtosecond period from the capability register, enables the main counter and exposes a monotonic nanosecond time source (hpet_get_ns) far finer than the 100 Hz PIT. - drivers/char/lpt.c + include/drivers/lpt.h: IBM PC parallel port (LPT1) with the Centronics data/strobe handshake over ports 0x378/0x379/0x37A. - drivers/char/nvram.c + include/drivers/nvram.h: MC146818 CMOS NVRAM read/write over 0x70/0x71, preserving the NMI-disable bit, with checksum and hex dump. Wired all three into the [5/14] device-enumeration boot step and added LazyBox applets `hpet`, `lpt`, and `nvram`. Verified live under QEMU (screenshotted): HPET reports 100 MHz / 3 comparators / 10 ns period and its counter advances ~1.4 s of real time between two `hpet` runs; NVRAM dumps 128 bytes with a computed checksum; LPT1 detected at 0x378. Clean build on x86_64/aarch64/armv8i; 0 panics / 0 OOM. Co-Authored-By: Claude Opus 4.8 <[email protected]> Claude-Session: https://claude.ai/code/session_01Fh5z6V7nGPbHvqVG5p4CXX
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@@ -277,7 +277,8 @@ endif
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# Common Input/Display/Power/GPU/Networking Drivers
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CONFIG_SRCS-y += drivers/char/tty.c drivers/char/keyboard.c drivers/char/serial.c drivers/char/vga.c \
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drivers/input/mouse.c drivers/power/acpi.c drivers/power/cpufreq.c drivers/rtc/rtc.c drivers/sound/speaker.c \
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drivers/net/e1000e.c drivers/virtio/virtio_gpu.c drivers/virtio/virtio_input.c
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drivers/net/e1000e.c drivers/virtio/virtio_gpu.c drivers/virtio/virtio_input.c \
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drivers/timer/hpet.c drivers/char/lpt.c drivers/char/nvram.c
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# Userland & GUI Desktop Subsystem
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ifeq ($(CONFIG_USERLAND_LAZYBOX), y)
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@@ -0,0 +1,80 @@
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// IBM PC parallel port (LPT1) printer driver for SUB-OS.
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//
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// Implements the classic Centronics handshake: place a byte on the data lines,
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// wait for the peripheral to be ready (nBUSY high), then pulse the STROBE line.
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#include <drivers/lpt.h>
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#include <kernel/printk.h>
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#if defined(__x86_64__)
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#include <arch/x86_64/io.h>
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#define LPT1_DATA 0x378
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#define LPT1_STATUS 0x379 // bit7 nBUSY (1 = ready), bit6 nACK, bit5 PAPER, bit4 SELECT
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#define LPT1_CONTROL 0x37A // bit0 STROBE, bit1 AUTOLF, bit2 nINIT, bit3 SELECT
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#define LPT_STATUS_BUSY 0x80
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#define LPT_CTRL_STROBE 0x01
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#define LPT_CTRL_INIT 0x04
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#define LPT_CTRL_SELECT 0x08
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static bool g_present = false;
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static uint64_t g_bytes_written = 0;
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void lpt_init(void) {
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uint8_t status = inb(LPT1_STATUS);
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// A floating (unimplemented) port typically reads back all-ones.
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if (status == 0xFF) {
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g_present = false;
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printk(KERN_INFO "LPT: no parallel port at 0x%03X\n", LPT1_DATA);
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return;
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}
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// Bring the port out of reset and select the printer.
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outb(LPT1_CONTROL, LPT_CTRL_INIT | LPT_CTRL_SELECT);
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g_present = true;
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printk(ANSI_BRIGHT_GREEN "LPT: " ANSI_RESET
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"Parallel port LPT1 online at 0x%03X (status 0x%02X)\n", LPT1_DATA, status);
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}
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bool lpt_present(void) { return g_present; }
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uint8_t lpt_status(void) { return g_present ? inb(LPT1_STATUS) : 0xFF; }
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int lpt_putc(char c) {
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if (!g_present) return -1;
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// Wait (bounded) for the peripheral to raise nBUSY.
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int spins = 100000;
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while (spins-- > 0 && !(inb(LPT1_STATUS) & LPT_STATUS_BUSY)) {
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/* busy-wait */
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}
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outb(LPT1_DATA, (uint8_t)c);
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// Pulse STROBE low->high to latch the byte.
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uint8_t ctrl = inb(LPT1_CONTROL);
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outb(LPT1_CONTROL, ctrl | LPT_CTRL_STROBE);
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outb(LPT1_CONTROL, ctrl & ~LPT_CTRL_STROBE);
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g_bytes_written++;
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return 0;
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}
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int lpt_write(const char* buf, size_t len) {
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if (!g_present || !buf) return -1;
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int n = 0;
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for (size_t i = 0; i < len; i++) {
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if (lpt_putc(buf[i]) != 0) break;
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n++;
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}
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return n;
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}
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#else // Parallel port is an x86 platform device.
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void lpt_init(void) { }
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bool lpt_present(void) { return false; }
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int lpt_putc(char c) { (void)c; return -1; }
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int lpt_write(const char* buf, size_t len) { (void)buf; (void)len; return -1; }
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uint8_t lpt_status(void) { return 0xFF; }
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#endif
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@@ -0,0 +1,64 @@
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// CMOS / RTC NVRAM driver for SUB-OS.
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//
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// Reads and writes the MC146818 CMOS register file behind ports 0x70/0x71.
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// The NMI-disable bit (0x80) of the index port is preserved on every access so
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// this driver never inadvertently re-enables NMIs.
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#include <drivers/nvram.h>
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#include <kernel/printk.h>
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#if defined(__x86_64__)
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#include <arch/x86_64/io.h>
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#define CMOS_INDEX 0x70
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#define CMOS_DATA 0x71
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#define CMOS_NMI_DISABLE 0x80
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uint8_t nvram_read(uint8_t index) {
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uint8_t prev = inb(CMOS_INDEX) & CMOS_NMI_DISABLE;
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outb(CMOS_INDEX, prev | (index & 0x7F));
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return inb(CMOS_DATA);
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}
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void nvram_write(uint8_t index, uint8_t value) {
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uint8_t prev = inb(CMOS_INDEX) & CMOS_NMI_DISABLE;
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outb(CMOS_INDEX, prev | (index & 0x7F));
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outb(CMOS_DATA, value);
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}
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uint8_t nvram_checksum(void) {
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uint16_t sum = 0;
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for (int i = NVRAM_USER_START; i < NVRAM_SIZE; i++) {
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sum += nvram_read((uint8_t)i);
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}
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return (uint8_t)(sum & 0xFF);
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}
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void nvram_dump(void) {
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printk(ANSI_BRIGHT_CYAN "CMOS NVRAM (128 bytes):\n" ANSI_RESET);
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for (int row = 0; row < NVRAM_SIZE; row += 16) {
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printk(" %02X: ", row);
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for (int col = 0; col < 16; col++) {
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printk("%02X ", nvram_read((uint8_t)(row + col)));
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}
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printk("\n");
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}
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}
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void nvram_init(void) {
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// Byte 0x0F is the BIOS shutdown status; reading it proves the port works.
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uint8_t shutdown_status = nvram_read(0x0F);
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printk(ANSI_BRIGHT_GREEN "NVRAM: " ANSI_RESET
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"CMOS scratch RAM ready (%d bytes, checksum 0x%02X, shutdown-status 0x%02X)\n",
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NVRAM_SIZE, nvram_checksum(), shutdown_status);
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}
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#else // CMOS/RTC NVRAM is an x86 platform device.
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uint8_t nvram_read(uint8_t index) { (void)index; return 0; }
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void nvram_write(uint8_t index, uint8_t v){ (void)index; (void)v; }
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uint8_t nvram_checksum(void) { return 0; }
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void nvram_dump(void) { }
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void nvram_init(void) { }
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#endif
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@@ -0,0 +1,91 @@
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// High Precision Event Timer (HPET) driver for SUB-OS.
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//
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// Reads the HPET block memory-mapped at the standard base 0xFED00000 (as
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// exposed by QEMU). The general-capabilities register carries the counter
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// period in femtoseconds, from which the tick frequency and a nanosecond
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// timestamp are derived. The kernel identity-maps low physical memory, so the
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// MMIO block is reachable directly through its physical address.
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#include <drivers/hpet.h>
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#include <kernel/printk.h>
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#if defined(__x86_64__)
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#define HPET_BASE_PHYS 0xFED00000ULL
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#define HPET_REG_CAP_ID 0x000 // General Capabilities and ID (64-bit)
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#define HPET_REG_CONFIG 0x010 // General Configuration (64-bit)
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#define HPET_REG_COUNTER 0x0F0 // Main Counter Value (64-bit)
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#define HPET_CFG_ENABLE 0x1ULL // General Config bit 0: overall enable
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static volatile uint64_t* g_hpet = (volatile uint64_t*)HPET_BASE_PHYS;
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static bool g_available = false;
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static uint64_t g_period_fs = 0; // counter period in femtoseconds
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static uint64_t g_freq_hz = 0;
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static uint32_t g_num_timers = 0;
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static uint64_t g_base_counter = 0; // counter value captured at init
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static inline uint64_t hpet_rd(uint32_t off) {
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return g_hpet[off / sizeof(uint64_t)];
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}
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static inline void hpet_wr(uint32_t off, uint64_t val) {
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g_hpet[off / sizeof(uint64_t)] = val;
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}
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void hpet_init(void) {
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uint64_t caps = hpet_rd(HPET_REG_CAP_ID);
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// Period lives in the top 32 bits (femtoseconds per tick). A sane HPET has
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// a non-zero period below 100 ns (100,000,000 fs); anything else means the
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// block is absent or unmapped, so we decline rather than divide by zero.
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uint64_t period = caps >> 32;
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if (period == 0 || period > 100000000ULL) {
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g_available = false;
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printk(KERN_INFO "HPET: not present (capabilities=0x%llx)\n",
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(unsigned long long)caps);
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return;
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}
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g_period_fs = period;
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g_num_timers = (uint32_t)(((caps >> 8) & 0x1F) + 1);
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g_freq_hz = 1000000000000000ULL / g_period_fs; // 1e15 fs per second
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// Enable the main counter.
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hpet_wr(HPET_REG_CONFIG, hpet_rd(HPET_REG_CONFIG) | HPET_CFG_ENABLE);
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g_base_counter = hpet_rd(HPET_REG_COUNTER);
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g_available = true;
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printk(ANSI_BRIGHT_GREEN "HPET: " ANSI_RESET
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"High Precision Event Timer online (%llu Hz, %u comparators, period %llu fs)\n",
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(unsigned long long)g_freq_hz, g_num_timers,
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(unsigned long long)g_period_fs);
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}
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bool hpet_available(void) { return g_available; }
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uint64_t hpet_read_counter(void) {
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if (!g_available) return 0;
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return hpet_rd(HPET_REG_COUNTER);
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}
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uint64_t hpet_get_frequency_hz(void) { return g_freq_hz; }
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uint64_t hpet_get_ns(void) {
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if (!g_available) return 0;
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uint64_t ticks = hpet_rd(HPET_REG_COUNTER) - g_base_counter;
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// ns = ticks * period_fs / 1e6 ; group to avoid overflow on large counts.
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return (ticks / 1000000ULL) * g_period_fs + ((ticks % 1000000ULL) * g_period_fs) / 1000000ULL;
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}
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uint32_t hpet_num_timers(void) { return g_num_timers; }
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#else // Non-x86 targets: HPET is an x86 platform device.
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void hpet_init(void) { }
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bool hpet_available(void) { return false; }
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uint64_t hpet_read_counter(void) { return 0; }
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uint64_t hpet_get_frequency_hz(void) { return 0; }
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uint64_t hpet_get_ns(void) { return 0; }
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uint32_t hpet_num_timers(void) { return 0; }
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#endif
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@@ -0,0 +1,21 @@
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#ifndef _DRIVERS_HPET_H
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#define _DRIVERS_HPET_H
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// High Precision Event Timer (HPET) driver.
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//
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// The HPET is a memory-mapped, free-running up-counter defined by the
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// Intel/Microsoft HPET spec and emulated by QEMU at the standard base
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// 0xFED00000. It provides a monotonic high-resolution time source far finer
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// than the 100 Hz PIT tick.
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#include <stdint.h>
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#include <stdbool.h>
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void hpet_init(void);
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bool hpet_available(void);
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uint64_t hpet_read_counter(void); // raw main counter value
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uint64_t hpet_get_frequency_hz(void); // counter ticks per second
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uint64_t hpet_get_ns(void); // nanoseconds since HPET was enabled
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uint32_t hpet_num_timers(void); // comparator count reported by the block
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#endif // _DRIVERS_HPET_H
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@@ -0,0 +1,17 @@
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#ifndef _DRIVERS_LPT_H
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#define _DRIVERS_LPT_H
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// IBM PC parallel port (LPT1) printer driver. Centronics handshake over the
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// standard I/O ports 0x378 (data) / 0x379 (status) / 0x37A (control).
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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void lpt_init(void);
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bool lpt_present(void);
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int lpt_putc(char c); // 0 on success, -1 on timeout/absent
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int lpt_write(const char* buf, size_t len); // bytes written
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uint8_t lpt_status(void); // raw status register
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#endif // _DRIVERS_LPT_H
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@@ -0,0 +1,20 @@
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#ifndef _DRIVERS_NVRAM_H
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#define _DRIVERS_NVRAM_H
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// CMOS / RTC NVRAM driver. The MC146818-compatible RTC exposes 128 indexed
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// bytes behind ports 0x70 (index) / 0x71 (data); bytes 0x0E..0x7F are the
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// battery-backed scratch RAM used by the BIOS for configuration.
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#include <stdint.h>
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#include <stdbool.h>
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#define NVRAM_SIZE 128
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#define NVRAM_USER_START 0x0E // first non-RTC (scratch) byte
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void nvram_init(void);
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uint8_t nvram_read(uint8_t index);
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void nvram_write(uint8_t index, uint8_t value);
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uint8_t nvram_checksum(void); // simple sum over the scratch region
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void nvram_dump(void); // hex dump of all 128 bytes to the console
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#endif // _DRIVERS_NVRAM_H
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@@ -73,6 +73,9 @@
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#include <drivers/e1000e.h>
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#include <drivers/virtio_gpu.h>
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#include <drivers/cpufreq.h>
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#include <drivers/hpet.h>
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#include <drivers/nvram.h>
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#include <drivers/lpt.h>
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#include <drivers/virtio_input.h>
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#include <gui/gui.h>
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#include <init/init.h>
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@@ -128,6 +131,9 @@ static void subos_modular_core_boot(void) {
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xhci_init();
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hwmon_init();
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cpufreq_init();
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hpet_init();
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nvram_init();
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lpt_init();
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#endif
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canvas_init();
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pty_init();
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@@ -32,6 +32,9 @@
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#include <kernel/nt/ob.h>
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#include <kernel/nt/reg.h>
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#include <kernel/nt/io.h>
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#include <drivers/hpet.h>
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#include <drivers/nvram.h>
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#include <drivers/lpt.h>
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#include <kernel/sub_lang.h>
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#include <kernel/cpp_kernel.h>
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#include <userland/snake.h>
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@@ -715,6 +718,39 @@ static int applet_iodev(int argc, char** argv) {
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return 0;
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}
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static int applet_hpet(int argc, char** argv) {
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(void)argc; (void)argv;
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if (!hpet_available()) {
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printk("HPET: not available on this platform\n");
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return 1;
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}
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printk(ANSI_BRIGHT_CYAN "High Precision Event Timer:\n" ANSI_RESET);
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printk(" Frequency : %llu Hz\n", (unsigned long long)hpet_get_frequency_hz());
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printk(" Comparators: %u\n", hpet_num_timers());
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printk(" Main count : %llu\n", (unsigned long long)hpet_read_counter());
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printk(" Uptime : %llu ns since HPET enable\n", (unsigned long long)hpet_get_ns());
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return 0;
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}
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static int applet_nvram(int argc, char** argv) {
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(void)argc; (void)argv;
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nvram_dump();
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printk(" checksum(0x0E..0x7F) = 0x%02X\n", nvram_checksum());
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return 0;
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}
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static int applet_lpt(int argc, char** argv) {
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if (!lpt_present()) {
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printk("LPT: no parallel port present\n");
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return 1;
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}
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const char* text = (argc >= 2) ? argv[1] : "SUB-OS\n";
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int n = lpt_write(text, strlen(text));
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printk("LPT1: status=0x%02X, wrote %d byte(s) to the parallel port\n",
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lpt_status(), n);
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return 0;
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}
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static int applet_rand(int argc, char** argv) {
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int count = (argc >= 2) ? atoi(argv[1]) : 4;
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printk("Random Integers: ");
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@@ -2428,6 +2464,9 @@ static const lazybox_applet_t applets[] = {
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{"ntobj", applet_ntobj, "ntobj", "NT Object Manager stats/demo","Kernel"},
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{"reg", applet_reg, "reg query|add|set|stats", "NT configuration registry", "Kernel"},
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{"iodev", applet_iodev, "iodev", "NT I/O Manager devices & IRP","Kernel"},
|
||||
{"hpet", applet_hpet, "hpet", "High Precision Event Timer", "Hardware"},
|
||||
{"nvram", applet_nvram, "nvram", "Dump CMOS NVRAM bytes", "Hardware"},
|
||||
{"lpt", applet_lpt, "lpt [text]", "Send text to LPT1 parallel", "Hardware"},
|
||||
{"rand", applet_rand, "rand [count]", "Generate random numbers", "Crypto"},
|
||||
{"certcheck", applet_certcheck, "certcheck", "View X.509 kernel keyring", "Security"},
|
||||
{"capsh", applet_capsh, "capsh", "View process capabilities", "Security"},
|
||||
|
||||
Reference in new issue
Block a user