feat(arch): Add AArch64 / ARMv8i CPU support, cross-compilation & Linux Kconfig TUI

- Implement AArch64 HAL, vector table (16 aligned vectors), GICv2, Generic Timer, Stage-1 MMU (39-bit VA), PL011 UART
- Build unified multi-architecture abstraction layer in include/arch/arch.h
- Create interactive Linux-like Kconfig TUI menuconfig in scripts/kconfig/menuconfig.py
- Support make menuconfig, defconfig, x86_64_defconfig, aarch64_defconfig
- Update master Makefile for cross-compiling x86_64 (x86_64-elf-) and AArch64 (aarch64-linux-gnu-)
- Dynamic architecture awareness across printk, uname, neofetch, and LazyBox

arch/aarch64/drivers/uart_pl011.c

@@ -0,0 +1,38 @@
+#include <arch/aarch64/uart.h>
+#include <arch/aarch64/io.h>
+
+void uart_pl011_init(void) {
+    // Enable UART, TX, and RX (bits 0, 8, 9)
+    mmio_write32(PL011_UART0_BASE + UARTCR, (1 << 0) | (1 << 8) | (1 << 9));
+}
+
+void uart_pl011_putc(char c) {
+    if (c == '\n') {
+        while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_TXFF) {
+            __asm__ volatile("nop");
+        }
+        mmio_write32(PL011_UART0_BASE + UARTDR, '\r');
+    }
+    while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_TXFF) {
+        __asm__ volatile("nop");
+    }
+    mmio_write32(PL011_UART0_BASE + UARTDR, (uint32_t)(uint8_t)c);
+}
+
+void uart_pl011_puts(const char* str) {
+    if (!str) return;
+    while (*str) {
+        uart_pl011_putc(*str++);
+    }
+}
+
+char uart_pl011_getc(void) {
+    while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_RXFE) {
+        __asm__ volatile("wfe");
+    }
+    return (char)(mmio_read32(PL011_UART0_BASE + UARTDR) & 0xFF);
+}
+
+int uart_pl011_has_data(void) {
+    return !(mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_RXFE);
+}