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feat(sched): Weave tiered scheduler with real kernel-thread context switching
Replace the state-relabel-only round-robin with the SUB-OS "Weave" scheduler backed by a genuine callee-saved context switch. Threads now actually run on their own kernel stacks instead of merely having their state field rewritten. What was implemented: - sub_ctx_switch(): per-arch assembly (arch/x86_64/cpu/switch.asm, arch/aarch64/cpu/switch.S, arch/armv8i/cpu/switch.S) that saves/restores the callee-saved register set (+ flags on x86_64) on each thread's own stack, plus a first-run trampoline (sub_thread_trampoline) that launches a freshly forged thread frame with entry/arg in callee-saved registers. - task_forge_frame(): builds the initial saved-context frame per arch so the very first switch into a new thread lands on the trampoline; task_t gains a pointer-sized ctx_sp so the same struct works on 64- and 32-bit. - Weave policy (kernel/sched.c): WEAVE_NLANES priority lanes, always dispatch the lowest non-empty lane round-robin; a task that yields voluntarily is woven UP a lane (interactive), one preempted after burning its quantum is woven DOWN (CPU-bound). Cooperative switching (sched_yield / task_exit) is always live; timer-driven preemption is gated behind sched_set_preempt() and left disarmed for now. - task_exit() now switches to the next runnable thread via sched_exit_current() instead of spinning/halting. - Boot-time weave_selftest() (x86_64) and sched_dump() diagnostics. How it was verified: - Builds clean for all three targets: x86_64 (CROSS_COMPILE=x86_64-linux-gnu-, RUSTC="rustc --target x86_64-unknown-none"), aarch64, armv8i. No new warnings; the new x86_64 asm carries a .note.GNU-stack section. - Booted x86_64 under QEMU (TCG): the self-test runs three cooperative kernel threads to completion on separate stacks with the expected 1->2->3 round-robin interleave, reports "20 real context switches, 3/3 workers exited", returns cleanly to the boot thread, and boot proceeds normally to ring-3 init and the shell. No fault/panic. Left unverified: - The aarch64/armv8i sub_ctx_switch frames build and link but are not yet boot-tested on their QEMU targets (tracked in docs/AUTODEV_ROADMAP.md). - Timer preemption path is implemented but disarmed; exited kernel threads currently leak their stack (reaper is next in the backlog). Co-Authored-By: Claude Opus 4.8 <[email protected]> Claude-Session: https://claude.ai/code/session_01Jk6K69yGS7zYgvoWd6nJxQ
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@@ -10,11 +10,56 @@ static task_t* current_task = NULL;
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static task_t kernel_idle_task;
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static LIST_HEAD(global_tasks);
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static void task_wrapper(task_entry_fn_t entry, void* arg) {
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if (entry) {
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entry(arg);
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}
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task_exit(0);
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/* Per-arch context switch primitives (see arch/<arch>/cpu/switch.*). */
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extern void sub_ctx_switch(void** save_sp, void* load_sp);
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extern void sub_thread_trampoline(void);
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/* Retire the running thread and switch to the next runnable one (sched.c). */
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extern void sched_exit_current(void);
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/*
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* Forge the initial saved-context frame for a brand-new thread so that the
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* first switch into it lands on sub_thread_trampoline with the entry function
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* and its argument sitting in the callee-saved registers the trampoline reads.
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* The exact word layout mirrors the pop/ldp/pop sequence in each arch's
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* sub_ctx_switch, so the two must be kept in lockstep.
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*/
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static void* task_forge_frame(uint64_t stack_base, size_t stack_size,
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task_entry_fn_t entry, void* arg) {
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#if defined(__x86_64__)
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uint64_t top = (stack_base + stack_size) & ~0xFULL; /* 16-byte aligned */
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uint64_t* sp = (uint64_t*)top;
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*(--sp) = (uint64_t)&sub_thread_trampoline; /* ret target */
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*(--sp) = 0; /* rbp */
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*(--sp) = 0; /* rbx */
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*(--sp) = (uint64_t)entry; /* r12 -> entry */
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*(--sp) = (uint64_t)arg; /* r13 -> arg */
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*(--sp) = 0; /* r14 */
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*(--sp) = 0; /* r15 */
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*(--sp) = 0x2; /* rflags, IF clear */
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return (void*)sp;
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#elif defined(__aarch64__) || defined(__arm64__)
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uint64_t top = (stack_base + stack_size) & ~0xFULL;
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uint64_t* sp = (uint64_t*)top;
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sp -= 12; /* x19..x30 */
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sp[0] = (uint64_t)entry; /* x19 -> entry */
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sp[1] = (uint64_t)arg; /* x20 -> arg */
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for (int i = 2; i <= 10; i++) sp[i] = 0; /* x21..x28, x29(fp) */
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sp[11] = (uint64_t)&sub_thread_trampoline; /* x30(lr) -> trampoline */
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return (void*)sp;
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#elif defined(__arm__)
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uint32_t top = (uint32_t)((stack_base + stack_size) & ~0x7ULL);
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uint32_t* sp = (uint32_t*)top;
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sp -= 9; /* r4..r11, lr */
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sp[0] = (uint32_t)(uintptr_t)entry; /* r4 -> entry */
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sp[1] = (uint32_t)(uintptr_t)arg; /* r5 -> arg */
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for (int i = 2; i <= 7; i++) sp[i] = 0; /* r6..r11 */
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sp[8] = (uint32_t)(uintptr_t)&sub_thread_trampoline; /* lr */
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return (void*)sp;
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#else
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(void)stack_base; (void)stack_size; (void)entry; (void)arg;
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return NULL;
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#endif
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}
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task_t* task_create(const char* name, task_entry_fn_t entry, void* arg, int priority) {
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@@ -37,14 +82,10 @@ task_t* task_create(const char* name, task_entry_fn_t entry, void* arg, int prio
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return NULL;
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}
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uint64_t* stack_top = (uint64_t*)(task->stack_base + task->stack_size);
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// Set up initial stack frame for AMD64
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*(--stack_top) = (uint64_t)arg; // RDI (arg)
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*(--stack_top) = (uint64_t)entry; // RSI (entry function)
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*(--stack_top) = (uint64_t)task_wrapper; // RIP
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task->rsp = (uint64_t)stack_top;
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// Forge the initial saved-register frame so the first context switch into
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// this thread lands on the trampoline with entry/arg in place.
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task->ctx_sp = task_forge_frame(task->stack_base, task->stack_size, entry, arg);
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task->rsp = (uint64_t)(uintptr_t)task->ctx_sp;
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INIT_LIST_HEAD(&task->list);
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INIT_LIST_HEAD(&task->all_list);
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@@ -59,8 +100,9 @@ void task_exit(int exit_code) {
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if (current_task && current_task->pid != 0) {
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current_task->exit_code = exit_code;
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current_task->state = TASK_STATE_DEAD;
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sched_remove_task(current_task);
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sched_yield();
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current_task->weave_on = 0;
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sched_exit_current(); // switches to the next runnable thread; only
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// falls through here if nothing else is runnable
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}
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while (1) {
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arch_halt();
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