feat(drivers): Implement NVMe PCIe SSD, AHCI SATA, Realtek RTL8139, Intel HD Audio (HDA), and USB 3.0 xHCI drivers + lsdev/lsblk tools

include/drivers/ahci.h

@@ -0,0 +1,75 @@
+#ifndef _DRIVERS_AHCI_H
+#define _DRIVERS_AHCI_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#define AHCI_PCI_CLASS    0x01
+#define AHCI_PCI_SUBCLASS 0x06
+#define AHCI_PCI_PROGIF   0x01
+
+#define HBA_PORT_IPM_ACTIVE  1
+#define HBA_PORT_DET_PRESENT 3
+
+#define AHCI_DEV_NULL   0
+#define AHCI_DEV_SATA   1
+#define AHCI_DEV_SEMB   2
+#define AHCI_DEV_PM     3
+#define AHCI_DEV_SATAPI 4
+
+typedef volatile struct {
+    uint32_t clb;
+    uint32_t clbu;
+    uint32_t fb;
+    uint32_t fbu;
+    uint32_t is;
+    uint32_t ie;
+    uint32_t cmd;
+    uint32_t rsv0;
+    uint32_t tfd;
+    uint32_t sig;
+    uint32_t ssts;
+    uint32_t sctl;
+    uint32_t serr;
+    uint32_t sact;
+    uint32_t ci;
+    uint32_t sntf;
+    uint32_t fbs;
+    uint32_t rsv1[11];
+    uint32_t vendor[4];
+} __attribute__((packed)) hba_port_t;
+
+typedef volatile struct {
+    uint32_t cap;
+    uint32_t ghc;
+    uint32_t is;
+    uint32_t pi;
+    uint32_t vs;
+    uint32_t ccc_ctl;
+    uint32_t ccc_pts;
+    uint32_t em_loc;
+    uint32_t em_ctl;
+    uint32_t cap2;
+    uint32_t bohc;
+    uint8_t  rsv[0xA0 - 0x2C];
+    uint8_t  vendor[0x100 - 0xA0];
+    hba_port_t ports[32];
+} __attribute__((packed)) hba_mem_t;
+
+typedef struct {
+    char     model[40];
+    char     serial[20];
+    uint64_t total_sectors;
+    uint32_t sector_size;
+    uint8_t  port_num;
+    bool     present;
+} ahci_device_info_t;
+
+bool ahci_init(void);
+bool ahci_is_detected(void);
+const ahci_device_info_t* ahci_get_port_info(uint8_t port);
+int  ahci_read_blocks(uint8_t port, uint64_t lba, uint32_t count, void* buffer);
+int  ahci_write_blocks(uint8_t port, uint64_t lba, uint32_t count, const void* buffer);
+
+#endif // _DRIVERS_AHCI_H

include/drivers/nvme.h

@@ -0,0 +1,77 @@
+#ifndef _DRIVERS_NVME_H
+#define _DRIVERS_NVME_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#define NVME_PCI_CLASS    0x01
+#define NVME_PCI_SUBCLASS 0x08
+#define NVME_PCI_PROGIF   0x02
+
+#define NVME_REG_CAP   0x0000 // Controller Capabilities
+#define NVME_REG_VS    0x0008 // Version
+#define NVME_REG_INTMS 0x000C // Interrupt Mask Set
+#define NVME_REG_INTMC 0x0010 // Interrupt Mask Clear
+#define NVME_REG_CC    0x0014 // Controller Configuration
+#define NVME_REG_CSTS  0x001C // Controller Status
+#define NVME_REG_AQA   0x0024 // Admin Queue Attributes
+#define NVME_REG_ASQ   0x0028 // Admin Submission Queue Base
+#define NVME_REG_ACQ   0x0030 // Admin Completion Queue Base
+
+#define NVME_OP_ADMIN_DELETE_SQ 0x00
+#define NVME_OP_ADMIN_CREATE_SQ 0x01
+#define NVME_OP_ADMIN_GET_LOG   0x02
+#define NVME_OP_ADMIN_DELETE_CQ 0x04
+#define NVME_OP_ADMIN_CREATE_CQ 0x05
+#define NVME_OP_ADMIN_IDENTIFY  0x06
+
+#define NVME_OP_NVM_FLUSH 0x00
+#define NVME_OP_NVM_WRITE 0x01
+#define NVME_OP_NVM_READ  0x02
+
+typedef struct {
+    uint8_t  opcode;
+    uint8_t  flags;
+    uint16_t cid;
+    uint32_t nsid;
+    uint64_t reserved;
+    uint64_t mptr;
+    uint64_t dptr_prp1;
+    uint64_t dptr_prp2;
+    uint32_t cdw10;
+    uint32_t cdw11;
+    uint32_t cdw12;
+    uint32_t cdw13;
+    uint32_t cdw14;
+    uint32_t cdw15;
+} __attribute__((packed)) nvme_sqe_t;
+
+typedef struct {
+    uint32_t cdw0;
+    uint32_t reserved;
+    uint16_t sq_head;
+    uint16_t sq_id;
+    uint16_t cid;
+    uint16_t status;
+} __attribute__((packed)) nvme_cqe_t;
+
+typedef struct {
+    char     model[40];
+    char     serial[20];
+    char     firmware[8];
+    uint64_t total_capacity_bytes;
+    uint64_t total_sectors;
+    uint32_t sector_size;
+    uint32_t max_transfer_sectors;
+    uint32_t queue_depth;
+    bool     initialized;
+} nvme_device_info_t;
+
+bool nvme_init(void);
+bool nvme_is_detected(void);
+const nvme_device_info_t* nvme_get_info(void);
+int  nvme_read_blocks(uint64_t lba, uint32_t count, void* buffer);
+int  nvme_write_blocks(uint64_t lba, uint32_t count, const void* buffer);
+
+#endif // _DRIVERS_NVME_H

include/drivers/rtl8139.h

@@ -0,0 +1,41 @@
+#ifndef _DRIVERS_RTL8139_H
+#define _DRIVERS_RTL8139_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#define RTL8139_VENDOR_ID 0x10EC
+#define RTL8139_DEVICE_ID 0x8139
+
+#define RTL8139_REG_MAC0   0x00
+#define RTL8139_REG_MAR0   0x08
+#define RTL8139_REG_TSD0   0x10
+#define RTL8139_REG_TSAD0  0x20
+#define RTL8139_REG_RBSTART 0x30
+#define RTL8139_REG_CR     0x37
+#define RTL8139_REG_CAPR   0x38
+#define RTL8139_REG_CBR    0x3A
+#define RTL8139_REG_IMR    0x3C
+#define RTL8139_REG_ISR    0x3E
+#define RTL8139_REG_TCR    0x40
+#define RTL8139_REG_RCR    0x44
+
+typedef struct {
+    uint8_t  mac[6];
+    uint16_t io_base;
+    uint32_t rx_buffer_phys;
+    uint8_t* rx_buffer;
+    uint32_t tx_buffer_phys[4];
+    uint8_t* tx_buffers[4];
+    uint8_t  tx_cur;
+    bool     initialized;
+} rtl8139_device_t;
+
+bool rtl8139_init(void);
+bool rtl8139_is_detected(void);
+void rtl8139_get_mac(uint8_t* mac_out);
+int  rtl8139_send_packet(const uint8_t* packet, uint16_t length);
+void rtl8139_handle_interrupt(void);
+
+#endif // _DRIVERS_RTL8139_H

include/drivers/xhci.h

@@ -0,0 +1,25 @@
+#ifndef _DRIVERS_XHCI_H
+#define _DRIVERS_XHCI_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#define XHCI_PCI_CLASS    0x0C
+#define XHCI_PCI_SUBCLASS 0x03
+#define XHCI_PCI_PROGIF   0x30
+
+typedef struct {
+    uint8_t  cap_length;
+    uint16_t hci_version;
+    uint32_t max_slots;
+    uint32_t max_ports;
+    uint32_t max_interrupters;
+    bool     initialized;
+} xhci_controller_info_t;
+
+bool xhci_init(void);
+bool xhci_is_detected(void);
+const xhci_controller_info_t* xhci_get_info(void);
+
+#endif // _DRIVERS_XHCI_H