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subhobhai943
7b646c8cc4
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
24 lines
494 B
C
24 lines
494 B
C
#ifndef _ARCH_ARMV8I_ARCH_H
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#define _ARCH_ARMV8I_ARCH_H
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#include <stdint.h>
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#include <stdbool.h>
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#define ARMV8I_PAGE_SIZE 4096
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// Mode bits in CPSR
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#define CPSR_MODE_USR 0x10
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#define CPSR_MODE_FIQ 0x11
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#define CPSR_MODE_IRQ 0x12
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#define CPSR_MODE_SVC 0x13
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#define CPSR_MODE_MON 0x16
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#define CPSR_MODE_ABT 0x17
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#define CPSR_MODE_HYP 0x1A
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#define CPSR_MODE_UND 0x1B
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#define CPSR_MODE_SYS 0x1F
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#define CPSR_IRQ_DISABLE (1 << 7)
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#define CPSR_FIQ_DISABLE (1 << 6)
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#endif // _ARCH_ARMV8I_ARCH_H
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