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subhobhai943andClaude Opus 4.8
0a874341c6
Kernel threads were only ever switched cooperatively (sched_yield, task_exit); a thread that never yielded held the CPU forever. The Weave scheduler now preempts from the PIT tick, so CPU-bound threads are time-sliced. Deferred switch, not mid-handler: - sched_tick() no longer switches. It charges the running quantum and, when it is spent, only raises weave_need_resched. The switch happens at IRQ return in the new sched_preempt_on_return(), called from the x86_64 dispatcher after the PIC EOI. That keeps the tick path re-entrancy-safe (the EOI is already out, so the PIC keeps delivering) and lets the preempted thread unwind through the normal iretq on its own kernel stack. Interrupt-atomic scheduler state: - The plain weave_lock is not IRQ-safe, so a tick landing mid-mutation would deadlock. weave_lock sections now mask interrupts (arch_irq_save/restore, added to arch.h for all three arches) so the timer can never fire inside them, and weave_rotate holds them masked across the pick and the register swap so the switch is one indivisible step. Preemption-disable count: - sched_preempt_disable/enable gate the tick and the return-path switch so a preemptive switch cannot land while a plain (non-IRQ-safe) spinlock is held. printk wraps its critical section with it, closing the most common hazard; other locks are a documented follow-up. Fresh threads opt into interrupts at entry so they are preemptible from birth without changing the cooperative early-boot self-test, which still runs with interrupts masked and is unchanged (20 switches, 3/3 workers). Verified on x86_64 under QEMU: a new boot-time self-test arms preemption and two threads that NEVER yield are forced to share the CPU -- 20 involuntary switches, both advance and are woven down to the CPU-bound lanes -- then boot proceeds cleanly to ring-3 /sbin/init and the shell with zero faults. aarch64 and armv8i still build; preemption is wired into the x86_64 IRQ path only, so those stay cooperative for now (their switch asm already exists). Co-Authored-By: Claude Opus 4.8 <[email protected]> Claude-Session: https://claude.ai/code/session_0161Jh7uCEMLYEMNPsjC1LKf
115 lines
3.5 KiB
C
115 lines
3.5 KiB
C
#include <arch/x86_64/isr.h>
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#include <arch/x86_64/idt.h>
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#include <arch/x86_64/pic.h>
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#include <kernel/printk.h>
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#include <kernel/panic.h>
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#include <kernel/exec.h>
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#include <kernel/sched.h>
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#include <lib/string.h>
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extern void* isr_stub_table[48];
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static isr_handler_t interrupt_handlers[256];
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static const char* exception_messages[32] = {
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"Division By Zero",
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"Debug",
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"Non-Maskable Interrupt",
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"Breakpoint",
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"Into Detected Overflow",
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"Out of Bounds",
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"Invalid Opcode",
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"No Coprocessor",
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"Double Fault",
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"Coprocessor Segment Overrun",
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"Bad TSS",
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"Segment Not Present",
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"Stack Fault",
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"General Protection Fault",
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"Page Fault",
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"Unknown Interrupt",
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"Coprocessor Fault",
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"Alignment Check",
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"Machine Check",
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"SIMD Floating-Point Exception",
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"Virtualization Exception",
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"Control Protection Exception",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Reserved",
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"Hypervisor Injection Exception",
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"VMM Communication Exception",
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"Security Exception",
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"Reserved"
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};
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void isr_register_handler(uint8_t int_no, isr_handler_t handler) {
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interrupt_handlers[int_no] = handler;
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}
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void isr_unregister_handler(uint8_t int_no) {
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interrupt_handlers[int_no] = NULL;
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}
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void isr_handler_common(registers_t* regs) {
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if (regs->int_no < 32) {
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/* A page fault reports the offending address in CR2; everything else
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* is best described by where it was executing. */
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uint64_t fault_addr = regs->rip;
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if (regs->int_no == 14) {
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__asm__ volatile("mov %%cr2, %0" : "=r"(fault_addr));
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}
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/*
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* CS still carries the privilege level the fault was taken from. A
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* ring 3 fault is the process's problem, not the kernel's: report it
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* and tear that process down instead of bringing the machine down
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* with it.
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*/
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if ((regs->cs & 3) == 3 && uproc_current()) {
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printk(KERN_ERR "\n[USER FAULT] Vector %llu: %s (error 0x%llx) at rip=0x%llx\n",
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regs->int_no, exception_messages[regs->int_no],
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regs->error_code, regs->rip);
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uproc_fault(exception_messages[regs->int_no], fault_addr);
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}
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// CPU Exception Fault
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printk(KERN_EMERG "\n[EXCEPTION] Vector %llu: %s (Error code: 0x%llx)\n",
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regs->int_no, exception_messages[regs->int_no], regs->error_code);
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panic_with_regs(exception_messages[regs->int_no], regs);
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}
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if (interrupt_handlers[regs->int_no] != NULL) {
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interrupt_handlers[regs->int_no](regs);
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}
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// Acknowledge Hardware PIC Interrupts (IRQs 32-47)
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if (regs->int_no >= 32 && regs->int_no < 48) {
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pic_send_eoi((uint8_t)(regs->int_no - 32));
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/* Preemption point. The EOI is already out, so the PIC will keep
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* delivering to whichever thread we switch into. Switching here rather
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* than inside the handler keeps the tick path re-entrancy-safe. */
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sched_preempt_on_return();
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}
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}
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extern void isr_stub_default(void);
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void isr_init(void) {
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memset(interrupt_handlers, 0, sizeof(interrupt_handlers));
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// 1. Initialize all 256 gates to isr_stub_default
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for (int i = 0; i < 256; i++) {
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idt_set_gate(i, (void*)isr_stub_default, 0x8E);
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}
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// 2. Install dedicated CPU exception gates (0-31) and hardware IRQ gates (32-47)
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for (uint8_t i = 0; i < 48; i++) {
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idt_set_gate(i, isr_stub_table[i], 0x8E);
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}
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}
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