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https://github.com/subhobhai943/SUB-OS.git
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subhobhai943
70d5925b16
- Implement AArch64 HAL, vector table (16 aligned vectors), GICv2, Generic Timer, Stage-1 MMU (39-bit VA), PL011 UART - Build unified multi-architecture abstraction layer in include/arch/arch.h - Create interactive Linux-like Kconfig TUI menuconfig in scripts/kconfig/menuconfig.py - Support make menuconfig, defconfig, x86_64_defconfig, aarch64_defconfig - Update master Makefile for cross-compiling x86_64 (x86_64-elf-) and AArch64 (aarch64-linux-gnu-) - Dynamic architecture awareness across printk, uname, neofetch, and LazyBox
59 lines
2.2 KiB
C
59 lines
2.2 KiB
C
#include <arch/aarch64/cpu.h>
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#include <lib/string.h>
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#include <kernel/printk.h>
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static aarch64_cpu_info_t cpu_info;
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uint64_t aarch64_get_midr(void) {
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uint64_t midr;
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__asm__ volatile("mrs %0, midr_el1" : "=r"(midr));
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return midr;
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}
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uint64_t aarch64_get_mpidr(void) {
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uint64_t mpidr;
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__asm__ volatile("mrs %0, mpidr_el1" : "=r"(mpidr));
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return mpidr;
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}
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uint32_t aarch64_get_current_el(void) {
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uint64_t cur_el;
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__asm__ volatile("mrs %0, CurrentEL" : "=r"(cur_el));
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return (uint32_t)(cur_el >> 2);
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}
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void aarch64_cpu_init(void) {
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memset(&cpu_info, 0, sizeof(cpu_info));
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uint64_t midr = aarch64_get_midr();
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cpu_info.implementer = (uint32_t)((midr >> 24) & 0xFF);
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cpu_info.variant = (uint32_t)((midr >> 20) & 0x0F);
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cpu_info.architecture = (uint32_t)((midr >> 16) & 0x0F);
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cpu_info.part_num = (uint32_t)((midr >> 4) & 0xFFF);
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cpu_info.revision = (uint32_t)(midr & 0x0F);
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cpu_info.current_el = aarch64_get_current_el();
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if (cpu_info.implementer == 0x41) { // ARM Limited
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switch (cpu_info.part_num) {
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case 0xD03: strcpy(cpu_info.model_name, "ARM Cortex-A53 (ARMv8.0-A)"); break;
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case 0xD07: strcpy(cpu_info.model_name, "ARM Cortex-A57 (ARMv8.0-A)"); break;
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case 0xD08: strcpy(cpu_info.model_name, "ARM Cortex-A72 (ARMv8.0-A)"); break;
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case 0xD09: strcpy(cpu_info.model_name, "ARM Cortex-A73 (ARMv8.0-A)"); break;
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case 0xD0B: strcpy(cpu_info.model_name, "ARM Cortex-A76 (ARMv8.2-A)"); break;
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case 0xD40: strcpy(cpu_info.model_name, "ARM Neoverse-V1 (ARMv8.4-A)"); break;
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default: strcpy(cpu_info.model_name, "ARMv8-A Compatible 64-Bit Processor"); break;
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}
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} else if (cpu_info.implementer == 0x61) { // Apple Silicon
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strcpy(cpu_info.model_name, "Apple Silicon M-Series (ARMv8-A)");
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} else {
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strcpy(cpu_info.model_name, "Generic AArch64 / ARMv8 64-Bit Core");
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}
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printk(KERN_INFO "CPU: %s (Implementer: 0x%02x, Part: 0x%03x, EL%u)\n",
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cpu_info.model_name, cpu_info.implementer, cpu_info.part_num, cpu_info.current_el);
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}
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const aarch64_cpu_info_t* aarch64_get_cpu_info(void) {
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return &cpu_info;
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}
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