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subhobhai943
70d5925b16
- Implement AArch64 HAL, vector table (16 aligned vectors), GICv2, Generic Timer, Stage-1 MMU (39-bit VA), PL011 UART - Build unified multi-architecture abstraction layer in include/arch/arch.h - Create interactive Linux-like Kconfig TUI menuconfig in scripts/kconfig/menuconfig.py - Support make menuconfig, defconfig, x86_64_defconfig, aarch64_defconfig - Update master Makefile for cross-compiling x86_64 (x86_64-elf-) and AArch64 (aarch64-linux-gnu-) - Dynamic architecture awareness across printk, uname, neofetch, and LazyBox
72 lines
2.1 KiB
C
72 lines
2.1 KiB
C
#include <arch/aarch64/gic.h>
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#include <arch/aarch64/io.h>
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#include <lib/string.h>
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#include <kernel/printk.h>
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#define MAX_GIC_IRQS 256
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static gic_irq_handler_t irq_handlers[MAX_GIC_IRQS];
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void gic_init(void) {
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memset(irq_handlers, 0, sizeof(irq_handlers));
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// 1. Disable Distributor
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mmio_write32(GIC_DIST_BASE + GICD_CTLR, 0);
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// 2. Clear pending and enable default priorities
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uint32_t typer = mmio_read32(GIC_DIST_BASE + GICD_TYPER);
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uint32_t num_irqs = 32 * ((typer & 0x1F) + 1);
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if (num_irqs > MAX_GIC_IRQS) num_irqs = MAX_GIC_IRQS;
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for (uint32_t i = 32; i < num_irqs; i += 32) {
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mmio_write32(GIC_DIST_BASE + GICD_ICENABLER(i / 32), 0xFFFFFFFF);
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}
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for (uint32_t i = 0; i < num_irqs; i += 4) {
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mmio_write32(GIC_DIST_BASE + GICD_IPRIORITYR(i / 4), 0xA0A0A0A0);
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}
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for (uint32_t i = 32; i < num_irqs; i += 4) {
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mmio_write32(GIC_DIST_BASE + GICD_ITARGETSR(i / 4), 0x01010101); // Target Core 0
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}
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// 3. Enable Distributor
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mmio_write32(GIC_DIST_BASE + GICD_CTLR, 1);
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// 4. Enable CPU Interface
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mmio_write32(GIC_CPU_BASE + GICC_PMR, 0xF0); // Priority mask
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mmio_write32(GIC_CPU_BASE + GICC_CTLR, 1); // Enable signaling
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printk(KERN_INFO "GIC: ARM Generic Interrupt Controller v2 initialized (%u IRQ lines)\n", num_irqs);
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}
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void gic_enable_irq(uint32_t irq) {
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if (irq >= MAX_GIC_IRQS) return;
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mmio_write32(GIC_DIST_BASE + GICD_ISENABLER(irq / 32), (1U << (irq % 32)));
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}
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void gic_disable_irq(uint32_t irq) {
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if (irq >= MAX_GIC_IRQS) return;
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mmio_write32(GIC_DIST_BASE + GICD_ICENABLER(irq / 32), (1U << (irq % 32)));
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}
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void gic_register_handler(uint32_t irq, gic_irq_handler_t handler) {
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if (irq < MAX_GIC_IRQS) {
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irq_handlers[irq] = handler;
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gic_enable_irq(irq);
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}
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}
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void gic_handle_irq(void) {
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uint32_t iar = mmio_read32(GIC_CPU_BASE + GICC_IAR);
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uint32_t irq = iar & 0x3FF;
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if (irq < 1020) {
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if (irq_handlers[irq]) {
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irq_handlers[irq](irq);
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}
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// End of Interrupt (EOIR)
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mmio_write32(GIC_CPU_BASE + GICC_EOIR, iar);
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}
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}
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