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https://github.com/subhobhai943/SUB-OS.git
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subhobhai943
7b646c8cc4
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
62 lines
1.6 KiB
ArmAsm
62 lines
1.6 KiB
ArmAsm
/*
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* SUB-OS ARMv8i (AArch32 / 32-Bit ARMv8) Bootstrap Entry Point
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*/
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.syntax unified
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.arm
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.section ".text.boot"
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.global _start
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.global armv8i_entry
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_start:
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armv8i_entry:
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// 1. Enable VFP and NEON Coprocessors (CP10 & CP11 Full Access)
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mrc p15, 0, r0, c1, c0, 2 // Read CPACR
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orr r0, r0, #(0xF << 20) // Enable CP10 and CP11
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mcr p15, 0, r0, c1, c0, 2 // Write CPACR
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isb
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// Enable VFP extension run (FPEXC.EN = 1)
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mov r0, #(1 << 30)
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vmsr fpexc, r0
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// 2. Clear SCTLR.V bit (bit 13) to use VBAR for exception vectors
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mrc p15, 0, r0, c1, c0, 0 // Read SCTLR
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bic r0, r0, #(1 << 13) // Clear Hivecs (V=0)
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mcr p15, 0, r0, c1, c0, 0 // Write SCTLR
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isb
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// 3. Set Vector Base Address Register (VBAR)
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ldr r0, =vectors
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mcr p15, 0, r0, c12, c0, 0 // Write VBAR
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isb
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// 4. Setup Banked Stack Pointers for Exception Modes
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cpsid if, #0x12 // Switch to IRQ mode
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ldr sp, =irq_stack_top
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cpsid if, #0x17 // Switch to Abort mode
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ldr sp, =abt_stack_top
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cpsid if, #0x1B // Switch to Undefined mode
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ldr sp, =und_stack_top
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cpsid if, #0x13 // Switch back to Supervisor mode (SVC)
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ldr sp, =stack_top
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// 5. Zero out BSS section
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ldr r0, =__bss_start
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ldr r1, =__bss_end
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mov r2, #0
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.bss_loop:
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cmp r0, r1
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strlt r2, [r0], #4
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blt .bss_loop
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// 6. Branch to ARMv8i C Kernel Entry
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bl kernel_main_armv8i
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.hang:
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wfi
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b .hang
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