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subhobhai943
7b646c8cc4
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
#include <arch/armv8i/mmu.h>
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#include <arch/armv8i/io.h>
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#include <lib/string.h>
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#include <kernel/printk.h>
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static uint32_t __attribute__((aligned(16384))) l1_page_table[4096];
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void armv8i_mmu_init(void) {
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// 1. Identity map the entire 4GB flat space with 1MB sections
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for (uint32_t i = 0; i < 4096; i++) {
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uint32_t phys = i * 0x100000;
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l1_page_table[i] = phys | (3 << 10) | (2 << 0);
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}
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// 2. Set Domain Access Control Register (DACR = 0xFFFFFFFF: All Manager)
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uint32_t dacr = 0xFFFFFFFF;
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__asm__ volatile("mcr p15, 0, %0, c3, c0, 0" :: "r"(dacr));
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// 3. Set Translation Table Base Control Register (TTBCR = 0)
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uint32_t ttbcr = 0;
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__asm__ volatile("mcr p15, 0, %0, c2, c0, 2" :: "r"(ttbcr));
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// 4. Set Translation Table Base Register 0 (TTBR0)
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uint32_t ttbr0 = (uint32_t)l1_page_table;
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__asm__ volatile("mcr p15, 0, %0, c2, c0, 0" :: "r"(ttbr0));
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// 5. Invalidate TLB & ICache
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uint32_t zero = 0;
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__asm__ volatile("mcr p15, 0, %0, c8, c7, 0" :: "r"(zero));
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__asm__ volatile("mcr p15, 0, %0, c7, c5, 0" :: "r"(zero));
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isb();
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dsb();
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// 6. Enable MMU and Branch Prediction in SCTLR
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uint32_t sctlr;
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__asm__ volatile("mrc p15, 0, %0, c1, c0, 0" : "=r"(sctlr));
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sctlr |= (1 << 0) | (1 << 11);
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__asm__ volatile("mcr p15, 0, %0, c1, c0, 0" :: "r"(sctlr));
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isb();
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dsb();
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}
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