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subhobhai943
7b646c8cc4
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
38 lines
1.3 KiB
C
38 lines
1.3 KiB
C
#ifndef _ARCH_ARMV8I_GIC_H
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#define _ARCH_ARMV8I_GIC_H
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#include <stdint.h>
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#include <stdbool.h>
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#define GICD_BASE 0x08000000
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#define GICC_BASE 0x08010000
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// Distributor Registers
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#define GICD_CTLR (GICD_BASE + 0x000)
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#define GICD_TYPER (GICD_BASE + 0x004)
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#define GICD_IIDR (GICD_BASE + 0x008)
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#define GICD_ISENABLER(n) (GICD_BASE + 0x100 + ((n) * 4))
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#define GICD_ICENABLER(n) (GICD_BASE + 0x180 + ((n) * 4))
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#define GICD_ISPENDR(n) (GICD_BASE + 0x200 + ((n) * 4))
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#define GICD_ICPENDR(n) (GICD_BASE + 0x280 + ((n) * 4))
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#define GICD_IPRIORITYR(n) (GICD_BASE + 0x400 + ((n) * 4))
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#define GICD_ITARGETSR(n) (GICD_BASE + 0x800 + ((n) * 4))
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#define GICD_ICFGR(n) (GICD_BASE + 0xC00 + ((n) * 4))
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// CPU Interface Registers
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#define GICC_CTLR (GICC_BASE + 0x000)
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#define GICC_PMR (GICC_BASE + 0x004)
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#define GICC_BPR (GICC_BASE + 0x008)
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#define GICC_IAR (GICC_BASE + 0x00C)
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#define GICC_EOIR (GICC_BASE + 0x010)
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typedef void (*gic_irq_handler_t)(uint32_t irq);
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void gic_init(void);
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void gic_enable_irq(uint32_t irq);
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void gic_disable_irq(uint32_t irq);
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void gic_set_priority(uint32_t irq, uint8_t prio);
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void gic_register_handler(uint32_t irq, gic_irq_handler_t handler);
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#endif // _ARCH_ARMV8I_GIC_H
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