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78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
#ifndef _DRIVERS_NVME_H
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#define _DRIVERS_NVME_H
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#include <stdint.h>
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#include <stddef.h>
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#include <stdbool.h>
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#define NVME_PCI_CLASS 0x01
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#define NVME_PCI_SUBCLASS 0x08
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#define NVME_PCI_PROGIF 0x02
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#define NVME_REG_CAP 0x0000 // Controller Capabilities
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#define NVME_REG_VS 0x0008 // Version
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#define NVME_REG_INTMS 0x000C // Interrupt Mask Set
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#define NVME_REG_INTMC 0x0010 // Interrupt Mask Clear
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#define NVME_REG_CC 0x0014 // Controller Configuration
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#define NVME_REG_CSTS 0x001C // Controller Status
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#define NVME_REG_AQA 0x0024 // Admin Queue Attributes
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#define NVME_REG_ASQ 0x0028 // Admin Submission Queue Base
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#define NVME_REG_ACQ 0x0030 // Admin Completion Queue Base
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#define NVME_OP_ADMIN_DELETE_SQ 0x00
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#define NVME_OP_ADMIN_CREATE_SQ 0x01
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#define NVME_OP_ADMIN_GET_LOG 0x02
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#define NVME_OP_ADMIN_DELETE_CQ 0x04
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#define NVME_OP_ADMIN_CREATE_CQ 0x05
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#define NVME_OP_ADMIN_IDENTIFY 0x06
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#define NVME_OP_NVM_FLUSH 0x00
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#define NVME_OP_NVM_WRITE 0x01
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#define NVME_OP_NVM_READ 0x02
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typedef struct {
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uint8_t opcode;
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uint8_t flags;
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uint16_t cid;
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uint32_t nsid;
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uint64_t reserved;
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uint64_t mptr;
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uint64_t dptr_prp1;
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uint64_t dptr_prp2;
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uint32_t cdw10;
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uint32_t cdw11;
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uint32_t cdw12;
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uint32_t cdw13;
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uint32_t cdw14;
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uint32_t cdw15;
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} __attribute__((packed)) nvme_sqe_t;
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typedef struct {
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uint32_t cdw0;
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uint32_t reserved;
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uint16_t sq_head;
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uint16_t sq_id;
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uint16_t cid;
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uint16_t status;
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} __attribute__((packed)) nvme_cqe_t;
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typedef struct {
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char model[40];
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char serial[20];
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char firmware[8];
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uint64_t total_capacity_bytes;
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uint64_t total_sectors;
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uint32_t sector_size;
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uint32_t max_transfer_sectors;
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uint32_t queue_depth;
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bool initialized;
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} nvme_device_info_t;
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bool nvme_init(void);
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bool nvme_is_detected(void);
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const nvme_device_info_t* nvme_get_info(void);
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int nvme_read_blocks(uint64_t lba, uint32_t count, void* buffer);
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int nvme_write_blocks(uint64_t lba, uint32_t count, const void* buffer);
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#endif // _DRIVERS_NVME_H
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