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subhobhai943andClaude Opus 4.8
0a874341c6
Kernel threads were only ever switched cooperatively (sched_yield, task_exit); a thread that never yielded held the CPU forever. The Weave scheduler now preempts from the PIT tick, so CPU-bound threads are time-sliced. Deferred switch, not mid-handler: - sched_tick() no longer switches. It charges the running quantum and, when it is spent, only raises weave_need_resched. The switch happens at IRQ return in the new sched_preempt_on_return(), called from the x86_64 dispatcher after the PIC EOI. That keeps the tick path re-entrancy-safe (the EOI is already out, so the PIC keeps delivering) and lets the preempted thread unwind through the normal iretq on its own kernel stack. Interrupt-atomic scheduler state: - The plain weave_lock is not IRQ-safe, so a tick landing mid-mutation would deadlock. weave_lock sections now mask interrupts (arch_irq_save/restore, added to arch.h for all three arches) so the timer can never fire inside them, and weave_rotate holds them masked across the pick and the register swap so the switch is one indivisible step. Preemption-disable count: - sched_preempt_disable/enable gate the tick and the return-path switch so a preemptive switch cannot land while a plain (non-IRQ-safe) spinlock is held. printk wraps its critical section with it, closing the most common hazard; other locks are a documented follow-up. Fresh threads opt into interrupts at entry so they are preemptible from birth without changing the cooperative early-boot self-test, which still runs with interrupts masked and is unchanged (20 switches, 3/3 workers). Verified on x86_64 under QEMU: a new boot-time self-test arms preemption and two threads that NEVER yield are forced to share the CPU -- 20 involuntary switches, both advance and are woven down to the CPU-bound lanes -- then boot proceeds cleanly to ring-3 /sbin/init and the shell with zero faults. aarch64 and armv8i still build; preemption is wired into the x86_64 IRQ path only, so those stay cooperative for now (their switch asm already exists). Co-Authored-By: Claude Opus 4.8 <[email protected]> Claude-Session: https://claude.ai/code/session_0161Jh7uCEMLYEMNPsjC1LKf
171 lines
4.3 KiB
C
171 lines
4.3 KiB
C
#ifndef _ARCH_ARCH_H
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#define _ARCH_ARCH_H
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#include <stdint.h>
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#include <stdbool.h>
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#if defined(__x86_64__)
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#define ARCH_NAME "x86_64"
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#define ARCH_IS_64BIT 1
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#include <arch/x86_64/gdt.h>
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#include <arch/x86_64/idt.h>
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#include <arch/x86_64/isr.h>
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#include <arch/x86_64/pic.h>
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#include <arch/x86_64/pit.h>
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#include <arch/x86_64/cpuid.h>
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#include <arch/x86_64/paging.h>
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#include <arch/x86_64/io.h>
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static inline void arch_enable_interrupts(void) {
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__asm__ volatile("sti");
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}
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static inline void arch_disable_interrupts(void) {
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__asm__ volatile("cli");
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}
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/* Save the current interrupt-enable state and disable interrupts; restore puts
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* it back exactly. Used to make a critical section atomic against IRQ handlers
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* (e.g. the preemptive scheduler) without unconditionally re-enabling. */
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static inline unsigned long arch_irq_save(void) {
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unsigned long flags;
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__asm__ volatile("pushfq; pop %0; cli" : "=r"(flags) :: "memory");
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return flags;
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}
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static inline void arch_irq_restore(unsigned long flags) {
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__asm__ volatile("push %0; popfq" :: "r"(flags) : "memory", "cc");
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}
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static inline void arch_halt(void) {
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__asm__ volatile("hlt");
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}
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static inline void arch_wait_for_interrupt(void) {
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__asm__ volatile("sti; hlt");
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}
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static inline uint64_t arch_get_ticks(void) {
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return pit_get_ticks();
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}
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static inline void arch_sleep(uint32_t ms) {
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pit_sleep(ms);
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}
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#elif defined(__aarch64__) || defined(__arm64__)
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#define ARCH_NAME "aarch64"
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#define ARCH_IS_64BIT 1
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#include <arch/aarch64/arch.h>
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#include <arch/aarch64/cpu.h>
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#include <arch/aarch64/gic.h>
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#include <arch/aarch64/timer.h>
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#include <arch/aarch64/mmu.h>
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#include <arch/aarch64/uart.h>
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#include <arch/aarch64/io.h>
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static inline void arch_enable_interrupts(void) {
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__asm__ volatile("msr daifclr, #2" ::: "memory");
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}
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static inline void arch_disable_interrupts(void) {
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__asm__ volatile("msr daifset, #2" ::: "memory");
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}
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static inline unsigned long arch_irq_save(void) {
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unsigned long flags;
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__asm__ volatile("mrs %0, daif; msr daifset, #2" : "=r"(flags) :: "memory");
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return flags;
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}
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static inline void arch_irq_restore(unsigned long flags) {
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__asm__ volatile("msr daif, %0" :: "r"(flags) : "memory");
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}
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static inline void arch_halt(void) {
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__asm__ volatile("wfi");
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}
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static inline void arch_wait_for_interrupt(void) {
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__asm__ volatile("msr daifclr, #2; wfi" ::: "memory");
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}
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static inline uint64_t arch_get_ticks(void) {
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return aarch64_timer_get_ticks();
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}
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static inline void arch_sleep(uint32_t ms) {
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uint64_t count = (ms > 10) ? (ms / 10) : 1;
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uint64_t target = aarch64_timer_get_ticks() + count;
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while (aarch64_timer_get_ticks() < target) {
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__asm__ volatile("wfi");
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}
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}
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uint64_t pit_get_ticks(void);
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void pit_sleep(uint32_t ms);
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#elif defined(__arm__) || defined(__armv8i__)
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#define ARCH_NAME "armv8i"
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#define ARCH_IS_64BIT 0
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#include <arch/armv8i/arch.h>
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#include <arch/armv8i/cpu.h>
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#include <arch/armv8i/gic.h>
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#include <arch/armv8i/timer.h>
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#include <arch/armv8i/mmu.h>
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#include <arch/armv8i/uart.h>
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#include <arch/armv8i/io.h>
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static inline void arch_enable_interrupts(void) {
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__asm__ volatile("cpsie i" ::: "memory");
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}
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static inline void arch_disable_interrupts(void) {
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__asm__ volatile("cpsid i" ::: "memory");
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}
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static inline unsigned long arch_irq_save(void) {
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unsigned long flags;
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__asm__ volatile("mrs %0, cpsr; cpsid i" : "=r"(flags) :: "memory");
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return flags;
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}
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static inline void arch_irq_restore(unsigned long flags) {
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__asm__ volatile("msr cpsr_c, %0" :: "r"(flags) : "memory", "cc");
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}
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static inline void arch_halt(void) {
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__asm__ volatile("wfi");
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}
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static inline void arch_wait_for_interrupt(void) {
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__asm__ volatile("cpsie i; wfi" ::: "memory");
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}
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static inline uint64_t arch_get_ticks(void) {
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return armv8i_timer_get_ticks();
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}
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static inline void arch_sleep(uint32_t ms) {
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uint64_t count = (ms > 10) ? (ms / 10) : 1;
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uint64_t target = armv8i_timer_get_ticks() + count;
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while (armv8i_timer_get_ticks() < target) {
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__asm__ volatile("wfi");
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}
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}
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uint64_t pit_get_ticks(void);
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void pit_sleep(uint32_t ms);
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#else
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#error "Unsupported Target CPU Architecture!"
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#endif
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// Generic Architecture API
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void arch_early_init(void);
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void arch_init(void);
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const char* arch_get_name(void);
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uint32_t arch_get_cpu_id(void);
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#endif // _ARCH_ARCH_H
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