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subhobhai943
7b646c8cc4
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
88 lines
1.5 KiB
ArmAsm
88 lines
1.5 KiB
ArmAsm
/*
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* SUB-OS ARMv8i (AArch32) Exception Vector Table
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*/
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.syntax unified
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.arm
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.section ".vectors", "ax"
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.align 5
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.global vectors
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vectors:
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ldr pc, =reset_handler
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ldr pc, =undef_handler
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ldr pc, =svc_handler
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ldr pc, =pabt_handler
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ldr pc, =dabt_handler
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ldr pc, =hyp_handler
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ldr pc, =irq_handler
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ldr pc, =fiq_handler
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.macro SAVE_REGS
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sub sp, sp, #72
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stmia sp, {r0 - r12}
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str lr, [sp, #52]
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mrs r0, spsr
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str r0, [sp, #56]
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.endm
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.macro RESTORE_REGS
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ldr r0, [sp, #56]
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msr spsr_cxsf, r0
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ldr lr, [sp, #52]
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ldmia sp, {r0 - r12}
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add sp, sp, #72
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.endm
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reset_handler:
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b _start
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undef_handler:
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SAVE_REGS
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mov r0, sp
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bl armv8i_undef_handler
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RESTORE_REGS
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movs pc, lr
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svc_handler:
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SAVE_REGS
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mov r0, sp
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bl armv8i_svc_handler
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RESTORE_REGS
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movs pc, lr
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pabt_handler:
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sub lr, lr, #4
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SAVE_REGS
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mov r0, sp
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bl armv8i_pabt_handler
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RESTORE_REGS
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movs pc, lr
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dabt_handler:
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sub lr, lr, #8
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SAVE_REGS
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mov r0, sp
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bl armv8i_dabt_handler
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RESTORE_REGS
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movs pc, lr
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hyp_handler:
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b .
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irq_handler:
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sub lr, lr, #4
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SAVE_REGS
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mov r0, sp
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bl armv8i_irq_handler
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RESTORE_REGS
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movs pc, lr
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fiq_handler:
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sub lr, lr, #4
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SAVE_REGS
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mov r0, sp
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bl armv8i_fiq_handler
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RESTORE_REGS
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movs pc, lr
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