Files
SUB-OS/arch/armv8i/drivers/uart_pl011.c
T
subhobhai943 7b646c8cc4 feat(arch): Add armv8i (32-bit ARM/AArch32) architecture & complete TUI configurator
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain
- Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC)
- Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU
- Support PL011 UART for early console & interactive LazyBox TTY input
- Update Makefile with make armv8i_defconfig and automated cross-compilation
- Update scripts/kconfig/menuconfig.py with dedicated armv8i options
2026-08-18 11:13:23 +05:30

39 lines
1.0 KiB
C

#include <arch/armv8i/uart.h>
#include <arch/armv8i/io.h>
void uart_pl011_init(void) {
// Enable UART, TX, and RX (bits 0, 8, 9)
mmio_write32(PL011_UART0_BASE + UARTCR, (1 << 0) | (1 << 8) | (1 << 9));
}
void uart_pl011_putc(char c) {
if (c == '\n') {
while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_TXFF) {
__asm__ volatile("nop");
}
mmio_write32(PL011_UART0_BASE + UARTDR, '\r');
}
while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_TXFF) {
__asm__ volatile("nop");
}
mmio_write32(PL011_UART0_BASE + UARTDR, (uint32_t)(uint8_t)c);
}
void uart_pl011_puts(const char* str) {
if (!str) return;
while (*str) {
uart_pl011_putc(*str++);
}
}
char uart_pl011_getc(void) {
while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_RXFE) {
__asm__ volatile("wfe");
}
return (char)(mmio_read32(PL011_UART0_BASE + UARTDR) & 0xFF);
}
int uart_pl011_has_data(void) {
return !(mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_RXFE);
}