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- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
39 lines
1.0 KiB
C
39 lines
1.0 KiB
C
#include <arch/armv8i/uart.h>
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#include <arch/armv8i/io.h>
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void uart_pl011_init(void) {
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// Enable UART, TX, and RX (bits 0, 8, 9)
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mmio_write32(PL011_UART0_BASE + UARTCR, (1 << 0) | (1 << 8) | (1 << 9));
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}
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void uart_pl011_putc(char c) {
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if (c == '\n') {
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while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_TXFF) {
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__asm__ volatile("nop");
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}
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mmio_write32(PL011_UART0_BASE + UARTDR, '\r');
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}
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while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_TXFF) {
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__asm__ volatile("nop");
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}
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mmio_write32(PL011_UART0_BASE + UARTDR, (uint32_t)(uint8_t)c);
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}
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void uart_pl011_puts(const char* str) {
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if (!str) return;
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while (*str) {
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uart_pl011_putc(*str++);
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}
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}
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char uart_pl011_getc(void) {
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while (mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_RXFE) {
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__asm__ volatile("wfe");
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}
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return (char)(mmio_read32(PL011_UART0_BASE + UARTDR) & 0xFF);
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}
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int uart_pl011_has_data(void) {
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return !(mmio_read32(PL011_UART0_BASE + UARTFR) & UARTFR_RXFE);
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}
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