mirror of
https://github.com/subhobhai943/SUB-OS.git
synced 2026-10-25 16:52:29 +00:00
79 lines
1.7 KiB
C
79 lines
1.7 KiB
C
#include <arch/x86_64/pic.h>
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#include <arch/x86_64/io.h>
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#define PIC1_COMMAND 0x20
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#define PIC1_DATA 0x21
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#define PIC2_COMMAND 0xA0
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#define PIC2_DATA 0xA1
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#define PIC_EOI 0x20
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#define ICW1_INIT 0x10
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#define ICW1_ICW4 0x01
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#define ICW4_8086 0x01
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void pic_send_eoi(uint8_t irq) {
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if (irq >= 8) {
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outb(PIC2_COMMAND, PIC_EOI);
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}
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outb(PIC1_COMMAND, PIC_EOI);
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}
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void pic_init(void) {
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outb(PIC1_COMMAND, ICW1_INIT | ICW1_ICW4);
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io_wait();
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outb(PIC2_COMMAND, ICW1_INIT | ICW1_ICW4);
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io_wait();
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// Remap Master PIC to 0x20 (32), Slave PIC to 0x28 (40)
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outb(PIC1_DATA, 0x20);
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io_wait();
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outb(PIC2_DATA, 0x28);
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io_wait();
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outb(PIC1_DATA, 4); // Tell Master that Slave is at IRQ2
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io_wait();
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outb(PIC2_DATA, 2); // Tell Slave its cascade identity
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io_wait();
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outb(PIC1_DATA, ICW4_8086);
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io_wait();
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outb(PIC2_DATA, ICW4_8086);
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io_wait();
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// Mask all interrupts initially except Cascade (IRQ2)
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outb(PIC1_DATA, 0xFB);
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outb(PIC2_DATA, 0xFF);
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}
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void pic_set_mask(uint8_t irq) {
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uint16_t port;
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if (irq < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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irq -= 8;
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}
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uint8_t value = inb(port) | (1 << irq);
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outb(port, value);
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}
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void pic_clear_mask(uint8_t irq) {
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uint16_t port;
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if (irq < 8) {
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port = PIC1_DATA;
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} else {
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port = PIC2_DATA;
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irq -= 8;
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uint8_t master_val = inb(PIC1_DATA) & ~(1 << 2);
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outb(PIC1_DATA, master_val);
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}
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uint8_t value = inb(port) & ~(1 << irq);
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outb(port, value);
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}
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void pic_disable(void) {
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outb(PIC1_DATA, 0xFF);
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outb(PIC2_DATA, 0xFF);
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}
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