feat(sched): Preemptive Weave scheduling driven by the timer tick

Kernel threads were only ever switched cooperatively (sched_yield, task_exit);
a thread that never yielded held the CPU forever. The Weave scheduler now
preempts from the PIT tick, so CPU-bound threads are time-sliced.

Deferred switch, not mid-handler:
- sched_tick() no longer switches. It charges the running quantum and, when it
  is spent, only raises weave_need_resched. The switch happens at IRQ return in
  the new sched_preempt_on_return(), called from the x86_64 dispatcher after
  the PIC EOI. That keeps the tick path re-entrancy-safe (the EOI is already
  out, so the PIC keeps delivering) and lets the preempted thread unwind
  through the normal iretq on its own kernel stack.

Interrupt-atomic scheduler state:
- The plain weave_lock is not IRQ-safe, so a tick landing mid-mutation would
  deadlock. weave_lock sections now mask interrupts (arch_irq_save/restore,
  added to arch.h for all three arches) so the timer can never fire inside
  them, and weave_rotate holds them masked across the pick and the register
  swap so the switch is one indivisible step.

Preemption-disable count:
- sched_preempt_disable/enable gate the tick and the return-path switch so a
  preemptive switch cannot land while a plain (non-IRQ-safe) spinlock is held.
  printk wraps its critical section with it, closing the most common hazard;
  other locks are a documented follow-up.

Fresh threads opt into interrupts at entry so they are preemptible from birth
without changing the cooperative early-boot self-test, which still runs with
interrupts masked and is unchanged (20 switches, 3/3 workers).

Verified on x86_64 under QEMU: a new boot-time self-test arms preemption and
two threads that NEVER yield are forced to share the CPU -- 20 involuntary
switches, both advance and are woven down to the CPU-bound lanes -- then boot
proceeds cleanly to ring-3 /sbin/init and the shell with zero faults. aarch64
and armv8i still build; preemption is wired into the x86_64 IRQ path only, so
those stay cooperative for now (their switch asm already exists).

Co-Authored-By: Claude Opus 4.8 <[email protected]>
Claude-Session: https://claude.ai/code/session_0161Jh7uCEMLYEMNPsjC1LKf

arch/x86_64/cpu/isr.c

@@ -4,6 +4,7 @@
 #include <kernel/printk.h>
 #include <kernel/panic.h>
 #include <kernel/exec.h>
+#include <kernel/sched.h>
 #include <lib/string.h>
 
 extern void* isr_stub_table[48];
@@ -88,6 +89,11 @@ void isr_handler_common(registers_t* regs) {
     // Acknowledge Hardware PIC Interrupts (IRQs 32-47)
     if (regs->int_no >= 32 && regs->int_no < 48) {
         pic_send_eoi((uint8_t)(regs->int_no - 32));
+
+        /* Preemption point. The EOI is already out, so the PIC will keep
+         * delivering to whichever thread we switch into. Switching here rather
+         * than inside the handler keeps the tick path re-entrancy-safe. */
+        sched_preempt_on_return();
     }
 }