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feat(arch): Add AArch64 / ARMv8i CPU support, cross-compilation & Linux Kconfig TUI
- Implement AArch64 HAL, vector table (16 aligned vectors), GICv2, Generic Timer, Stage-1 MMU (39-bit VA), PL011 UART - Build unified multi-architecture abstraction layer in include/arch/arch.h - Create interactive Linux-like Kconfig TUI menuconfig in scripts/kconfig/menuconfig.py - Support make menuconfig, defconfig, x86_64_defconfig, aarch64_defconfig - Update master Makefile for cross-compiling x86_64 (x86_64-elf-) and AArch64 (aarch64-linux-gnu-) - Dynamic architecture awareness across printk, uname, neofetch, and LazyBox
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@@ -0,0 +1,65 @@
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#include <arch/arch.h>
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#include <arch/aarch64/cpu.h>
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#include <arch/aarch64/gic.h>
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#include <arch/aarch64/timer.h>
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#include <arch/aarch64/uart.h>
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#include <arch/aarch64/mmu.h>
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#include <arch/x86_64/cpuid.h>
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#include <kernel/printk.h>
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#include <lib/string.h>
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static cpu_info_t aarch64_compat_cpu;
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void arch_early_init(void) {
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uart_pl011_init();
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}
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void arch_init(void) {
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aarch64_cpu_init();
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gic_init();
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aarch64_timer_init(100);
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aarch64_mmu_init();
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// Populate compatibility CPU info structure for procfs
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memset(&aarch64_compat_cpu, 0, sizeof(aarch64_compat_cpu));
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const aarch64_cpu_info_t* info = aarch64_get_cpu_info();
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strncpy(aarch64_compat_cpu.vendor, "ARM Ltd", sizeof(aarch64_compat_cpu.vendor) - 1);
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strncpy(aarch64_compat_cpu.model, info->model_name, sizeof(aarch64_compat_cpu.model) - 1);
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aarch64_compat_cpu.has_fpu = true;
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arch_enable_interrupts();
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}
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const char* arch_get_name(void) {
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return "aarch64 (ARMv8-A)";
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}
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uint32_t arch_get_cpu_id(void) {
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return (uint32_t)(aarch64_get_mpidr() & 0xFF);
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}
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// Timer Compatibility Layer for Portable Drivers
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uint64_t pit_get_ticks(void) {
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return aarch64_timer_get_ticks();
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}
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void pit_sleep(uint32_t ms) {
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uint64_t count = (ms > 10) ? (ms / 10) : 1;
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uint64_t target = aarch64_timer_get_ticks() + count;
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while (aarch64_timer_get_ticks() < target) {
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__asm__ volatile("wfi");
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}
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}
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// Interrupt & CPUID Compatibility Stubs
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void isr_register_handler(uint8_t isr, void* handler) {
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(void)isr; (void)handler;
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}
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void pic_clear_mask(uint8_t irq) {
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(void)irq;
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}
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const cpu_info_t* cpuid_get_info(void) {
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return &aarch64_compat_cpu;
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}
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@@ -0,0 +1,58 @@
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#include <arch/aarch64/cpu.h>
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#include <lib/string.h>
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#include <kernel/printk.h>
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static aarch64_cpu_info_t cpu_info;
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uint64_t aarch64_get_midr(void) {
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uint64_t midr;
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__asm__ volatile("mrs %0, midr_el1" : "=r"(midr));
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return midr;
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}
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uint64_t aarch64_get_mpidr(void) {
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uint64_t mpidr;
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__asm__ volatile("mrs %0, mpidr_el1" : "=r"(mpidr));
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return mpidr;
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}
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uint32_t aarch64_get_current_el(void) {
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uint64_t cur_el;
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__asm__ volatile("mrs %0, CurrentEL" : "=r"(cur_el));
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return (uint32_t)(cur_el >> 2);
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}
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void aarch64_cpu_init(void) {
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memset(&cpu_info, 0, sizeof(cpu_info));
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uint64_t midr = aarch64_get_midr();
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cpu_info.implementer = (uint32_t)((midr >> 24) & 0xFF);
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cpu_info.variant = (uint32_t)((midr >> 20) & 0x0F);
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cpu_info.architecture = (uint32_t)((midr >> 16) & 0x0F);
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cpu_info.part_num = (uint32_t)((midr >> 4) & 0xFFF);
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cpu_info.revision = (uint32_t)(midr & 0x0F);
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cpu_info.current_el = aarch64_get_current_el();
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if (cpu_info.implementer == 0x41) { // ARM Limited
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switch (cpu_info.part_num) {
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case 0xD03: strcpy(cpu_info.model_name, "ARM Cortex-A53 (ARMv8.0-A)"); break;
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case 0xD07: strcpy(cpu_info.model_name, "ARM Cortex-A57 (ARMv8.0-A)"); break;
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case 0xD08: strcpy(cpu_info.model_name, "ARM Cortex-A72 (ARMv8.0-A)"); break;
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case 0xD09: strcpy(cpu_info.model_name, "ARM Cortex-A73 (ARMv8.0-A)"); break;
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case 0xD0B: strcpy(cpu_info.model_name, "ARM Cortex-A76 (ARMv8.2-A)"); break;
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case 0xD40: strcpy(cpu_info.model_name, "ARM Neoverse-V1 (ARMv8.4-A)"); break;
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default: strcpy(cpu_info.model_name, "ARMv8-A Compatible 64-Bit Processor"); break;
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}
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} else if (cpu_info.implementer == 0x61) { // Apple Silicon
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strcpy(cpu_info.model_name, "Apple Silicon M-Series (ARMv8-A)");
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} else {
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strcpy(cpu_info.model_name, "Generic AArch64 / ARMv8 64-Bit Core");
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}
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printk(KERN_INFO "CPU: %s (Implementer: 0x%02x, Part: 0x%03x, EL%u)\n",
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cpu_info.model_name, cpu_info.implementer, cpu_info.part_num, cpu_info.current_el);
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}
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const aarch64_cpu_info_t* aarch64_get_cpu_info(void) {
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return &cpu_info;
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}
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@@ -0,0 +1,42 @@
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#include <arch/aarch64/arch.h>
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#include <arch/aarch64/gic.h>
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#include <kernel/printk.h>
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void aarch64_sync_handler(aarch64_context_t* ctx) {
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uint64_t esr, elr, far;
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__asm__ volatile("mrs %0, esr_el1" : "=r"(esr));
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__asm__ volatile("mrs %0, elr_el1" : "=r"(elr));
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__asm__ volatile("mrs %0, far_el1" : "=r"(far));
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uint32_t ec = (esr >> 26) & 0x3F;
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printk(ANSI_BRIGHT_RED "\n[KERNEL PANIC] AArch64 Synchronous Exception!\n" ANSI_RESET);
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printk("ESR_EL1: 0x%016llx (EC: 0x%02x, ISS: 0x%08x)\n", esr, ec, (uint32_t)(esr & 0x01FFFFFF));
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printk("ELR_EL1 (PC): 0x%016llx FAR_EL1: 0x%016llx\n", elr, far);
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printk("Registers:\n");
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for (int i = 0; i < 30; i += 2) {
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printk(" X%02d: 0x%016llx X%02d: 0x%016llx\n", i, ctx->r[i], i + 1, ctx->r[i + 1]);
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}
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printk(" X30 (LR): 0x%016llx SP: 0x%016llx\n", ctx->r[30], ctx->sp);
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while (1) {
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__asm__ volatile("wfe");
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}
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}
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void aarch64_irq_handler(aarch64_context_t* ctx) {
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(void)ctx;
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gic_handle_irq();
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}
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void aarch64_fiq_handler(aarch64_context_t* ctx) {
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(void)ctx;
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printk(KERN_WARNING "AArch64: Unexpected FIQ caught\n");
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}
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void aarch64_serror_handler(aarch64_context_t* ctx) {
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(void)ctx;
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printk(ANSI_BRIGHT_RED "[KERNEL PANIC] AArch64 SError Interrupt caught!\n" ANSI_RESET);
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while (1) {
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__asm__ volatile("wfe");
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}
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}
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@@ -0,0 +1,71 @@
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#include <arch/aarch64/gic.h>
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#include <arch/aarch64/io.h>
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#include <lib/string.h>
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#include <kernel/printk.h>
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#define MAX_GIC_IRQS 256
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static gic_irq_handler_t irq_handlers[MAX_GIC_IRQS];
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void gic_init(void) {
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memset(irq_handlers, 0, sizeof(irq_handlers));
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// 1. Disable Distributor
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mmio_write32(GIC_DIST_BASE + GICD_CTLR, 0);
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// 2. Clear pending and enable default priorities
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uint32_t typer = mmio_read32(GIC_DIST_BASE + GICD_TYPER);
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uint32_t num_irqs = 32 * ((typer & 0x1F) + 1);
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if (num_irqs > MAX_GIC_IRQS) num_irqs = MAX_GIC_IRQS;
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for (uint32_t i = 32; i < num_irqs; i += 32) {
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mmio_write32(GIC_DIST_BASE + GICD_ICENABLER(i / 32), 0xFFFFFFFF);
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}
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for (uint32_t i = 0; i < num_irqs; i += 4) {
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mmio_write32(GIC_DIST_BASE + GICD_IPRIORITYR(i / 4), 0xA0A0A0A0);
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}
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for (uint32_t i = 32; i < num_irqs; i += 4) {
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mmio_write32(GIC_DIST_BASE + GICD_ITARGETSR(i / 4), 0x01010101); // Target Core 0
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}
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// 3. Enable Distributor
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mmio_write32(GIC_DIST_BASE + GICD_CTLR, 1);
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// 4. Enable CPU Interface
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mmio_write32(GIC_CPU_BASE + GICC_PMR, 0xF0); // Priority mask
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mmio_write32(GIC_CPU_BASE + GICC_CTLR, 1); // Enable signaling
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printk(KERN_INFO "GIC: ARM Generic Interrupt Controller v2 initialized (%u IRQ lines)\n", num_irqs);
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}
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void gic_enable_irq(uint32_t irq) {
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if (irq >= MAX_GIC_IRQS) return;
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mmio_write32(GIC_DIST_BASE + GICD_ISENABLER(irq / 32), (1U << (irq % 32)));
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}
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void gic_disable_irq(uint32_t irq) {
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if (irq >= MAX_GIC_IRQS) return;
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mmio_write32(GIC_DIST_BASE + GICD_ICENABLER(irq / 32), (1U << (irq % 32)));
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}
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void gic_register_handler(uint32_t irq, gic_irq_handler_t handler) {
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if (irq < MAX_GIC_IRQS) {
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irq_handlers[irq] = handler;
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gic_enable_irq(irq);
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}
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}
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void gic_handle_irq(void) {
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uint32_t iar = mmio_read32(GIC_CPU_BASE + GICC_IAR);
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uint32_t irq = iar & 0x3FF;
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if (irq < 1020) {
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if (irq_handlers[irq]) {
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irq_handlers[irq](irq);
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}
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// End of Interrupt (EOIR)
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mmio_write32(GIC_CPU_BASE + GICC_EOIR, iar);
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}
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}
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@@ -0,0 +1,49 @@
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#include <arch/aarch64/timer.h>
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#include <arch/aarch64/gic.h>
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#include <kernel/timer.h>
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#include <kernel/printk.h>
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static uint64_t timer_ticks = 0;
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static uint64_t timer_freq = 62500000; // Standard 62.5MHz QEMU virt frequency
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static uint32_t tick_interval = 0;
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void aarch64_timer_handle_irq(void) {
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timer_ticks++;
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// Reset next comparator interval
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__asm__ volatile("msr cntv_tval_el0, %0" :: "r"((uint64_t)tick_interval));
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// Call generic kernel timer tick
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timer_tick();
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}
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static void gic_timer_wrapper(uint32_t irq) {
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(void)irq;
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aarch64_timer_handle_irq();
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}
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void aarch64_timer_init(uint32_t freq_hz) {
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if (freq_hz == 0) freq_hz = 100;
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__asm__ volatile("mrs %0, cntfrq_el0" : "=r"(timer_freq));
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tick_interval = (uint32_t)(timer_freq / freq_hz);
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// Register with GIC (PPI 27 = Virtual Timer IRQ)
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gic_register_handler(ARCH_TIMER_VIRT_IRQ, gic_timer_wrapper);
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// Set countdown and enable virtual timer
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__asm__ volatile("msr cntv_tval_el0, %0" :: "r"((uint64_t)tick_interval));
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uint64_t ctl = 1; // Enable=1, IMASK=0
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__asm__ volatile("msr cntv_ctl_el0, %0" :: "r"(ctl));
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printk(KERN_INFO "Timer: ARM Generic Arch Timer active (%u Hz, Base Clock: %llu MHz)\n",
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freq_hz, timer_freq / 1000000);
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}
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uint64_t aarch64_timer_get_ticks(void) {
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return timer_ticks;
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}
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uint64_t aarch64_timer_get_freq(void) {
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return timer_freq;
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}
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@@ -0,0 +1,117 @@
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/*
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* SUB-OS AArch64 Exception Vector Table
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* 16 vectors aligned on 128-byte (0x80) boundaries
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*/
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.macro SAVE_ALL
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sub sp, sp, #272
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stp x0, x1, [sp, #0]
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stp x2, x3, [sp, #16]
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stp x4, x5, [sp, #32]
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stp x6, x7, [sp, #48]
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stp x8, x9, [sp, #64]
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stp x10, x11, [sp, #80]
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stp x12, x13, [sp, #96]
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stp x14, x15, [sp, #112]
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stp x16, x17, [sp, #128]
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stp x18, x19, [sp, #144]
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stp x20, x21, [sp, #160]
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stp x22, x23, [sp, #176]
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stp x24, x25, [sp, #192]
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stp x26, x27, [sp, #208]
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stp x28, x29, [sp, #224]
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mrs x0, elr_el1
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mrs x1, spsr_el1
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stp x30, x0, [sp, #240]
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str x1, [sp, #256]
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.endm
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.macro RESTORE_ALL
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ldr x1, [sp, #256]
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msr spsr_el1, x1
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ldp x30, x0, [sp, #240]
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msr elr_el1, x0
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ldp x28, x29, [sp, #224]
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ldp x26, x27, [sp, #208]
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ldp x24, x25, [sp, #192]
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ldp x22, x23, [sp, #176]
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ldp x20, x21, [sp, #160]
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ldp x18, x19, [sp, #144]
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ldp x16, x17, [sp, #128]
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ldp x14, x15, [sp, #112]
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ldp x12, x13, [sp, #96]
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ldp x10, x11, [sp, #80]
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ldp x8, x9, [sp, #64]
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ldp x6, x7, [sp, #48]
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ldp x4, x5, [sp, #32]
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ldp x2, x3, [sp, #16]
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ldp x0, x1, [sp, #0]
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add sp, sp, #272
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eret
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.endm
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.section ".vectors", "ax"
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.align 11
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.global vectors
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vectors:
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// 1. Current EL with SP0
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.align 7; b handle_sync_curr_sp0
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.align 7; b handle_irq_curr_sp0
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.align 7; b handle_fiq_curr_sp0
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.align 7; b handle_serror_curr_sp0
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// 2. Current EL with SPx
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.align 7; b handle_sync_curr_spx
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.align 7; b handle_irq_curr_spx
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.align 7; b handle_fiq_curr_spx
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.align 7; b handle_serror_curr_spx
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// 3. Lower EL using AArch64
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.align 7; b handle_sync_lower_aarch64
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.align 7; b handle_irq_lower_aarch64
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.align 7; b handle_fiq_lower_aarch64
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.align 7; b handle_serror_lower_aarch64
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// 4. Lower EL using AArch32
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.align 7; b handle_sync_lower_aarch32
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.align 7; b handle_irq_lower_aarch32
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.align 7; b handle_fiq_lower_aarch32
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.align 7; b handle_serror_lower_aarch32
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// Common Vector Handlers
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handle_sync_curr_sp0:
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handle_sync_curr_spx:
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handle_sync_lower_aarch64:
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handle_sync_lower_aarch32:
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SAVE_ALL
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mov x0, sp
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bl aarch64_sync_handler
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RESTORE_ALL
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handle_irq_curr_sp0:
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handle_irq_curr_spx:
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handle_irq_lower_aarch64:
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handle_irq_lower_aarch32:
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SAVE_ALL
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mov x0, sp
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bl aarch64_irq_handler
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RESTORE_ALL
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handle_fiq_curr_sp0:
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handle_fiq_curr_spx:
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handle_fiq_lower_aarch64:
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handle_fiq_lower_aarch32:
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SAVE_ALL
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mov x0, sp
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bl aarch64_fiq_handler
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RESTORE_ALL
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handle_serror_curr_sp0:
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handle_serror_curr_spx:
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handle_serror_lower_aarch64:
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||||
handle_serror_lower_aarch32:
|
||||
SAVE_ALL
|
||||
mov x0, sp
|
||||
bl aarch64_serror_handler
|
||||
RESTORE_ALL
|
||||
Reference in new issue
Block a user