feat(arch): Add AArch64 / ARMv8i CPU support, cross-compilation & Linux Kconfig TUI

- Implement AArch64 HAL, vector table (16 aligned vectors), GICv2, Generic Timer, Stage-1 MMU (39-bit VA), PL011 UART
- Build unified multi-architecture abstraction layer in include/arch/arch.h
- Create interactive Linux-like Kconfig TUI menuconfig in scripts/kconfig/menuconfig.py
- Support make menuconfig, defconfig, x86_64_defconfig, aarch64_defconfig
- Update master Makefile for cross-compiling x86_64 (x86_64-elf-) and AArch64 (aarch64-linux-gnu-)
- Dynamic architecture awareness across printk, uname, neofetch, and LazyBox

include/arch/aarch64/arch.h

@@ -0,0 +1,16 @@
+#ifndef _ARCH_AARCH64_ARCH_H
+#define _ARCH_AARCH64_ARCH_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef struct {
+    uint64_t r[31]; // X0 - X30
+    uint64_t sp;
+    uint64_t pc;
+    uint64_t pstate;
+} __attribute__((packed)) aarch64_context_t;
+
+void aarch64_init(void);
+
+#endif // _ARCH_AARCH64_ARCH_H

include/arch/aarch64/cpu.h

@@ -0,0 +1,24 @@
+#ifndef _ARCH_AARCH64_CPU_H
+#define _ARCH_AARCH64_CPU_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef struct {
+    uint32_t implementer;
+    uint32_t variant;
+    uint32_t architecture;
+    uint32_t part_num;
+    uint32_t revision;
+    char     model_name[64];
+    uint32_t current_el;
+    uint64_t core_frequency_hz;
+} aarch64_cpu_info_t;
+
+void aarch64_cpu_init(void);
+const aarch64_cpu_info_t* aarch64_get_cpu_info(void);
+uint32_t aarch64_get_current_el(void);
+uint64_t aarch64_get_midr(void);
+uint64_t aarch64_get_mpidr(void);
+
+#endif // _ARCH_AARCH64_CPU_H

include/arch/aarch64/gic.h

@@ -0,0 +1,34 @@
+#ifndef _ARCH_AARCH64_GIC_H
+#define _ARCH_AARCH64_GIC_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define GIC_DIST_BASE 0x08000000
+#define GIC_CPU_BASE  0x08010000
+
+// GIC Distributor Registers
+#define GICD_CTLR            0x000
+#define GICD_TYPER           0x004
+#define GICD_ISENABLER(n)   (0x100 + ((n) * 4))
+#define GICD_ICENABLER(n)   (0x180 + ((n) * 4))
+#define GICD_IPRIORITYR(n)  (0x400 + ((n) * 4))
+#define GICD_ITARGETSR(n)   (0x800 + ((n) * 4))
+#define GICD_ICFGR(n)       (0xC00 + ((n) * 4))
+
+// GIC CPU Interface Registers
+#define GICC_CTLR            0x0000
+#define GICC_PMR             0x0004
+#define GICC_BPR             0x0008
+#define GICC_IAR             0x000C
+#define GICC_EOIR            0x0010
+
+typedef void (*gic_irq_handler_t)(uint32_t irq);
+
+void gic_init(void);
+void gic_enable_irq(uint32_t irq);
+void gic_disable_irq(uint32_t irq);
+void gic_register_handler(uint32_t irq, gic_irq_handler_t handler);
+void gic_handle_irq(void);
+
+#endif // _ARCH_AARCH64_GIC_H

include/arch/aarch64/io.h

@@ -0,0 +1,95 @@
+#ifndef _ARCH_AARCH64_IO_H
+#define _ARCH_AARCH64_IO_H
+
+#include <stdint.h>
+
+static inline void mmio_write8(uintptr_t reg, uint8_t val) {
+    *(volatile uint8_t*)reg = val;
+}
+
+static inline uint8_t mmio_read8(uintptr_t reg) {
+    return *(volatile uint8_t*)reg;
+}
+
+static inline void mmio_write16(uintptr_t reg, uint16_t val) {
+    *(volatile uint16_t*)reg = val;
+}
+
+static inline uint16_t mmio_read16(uintptr_t reg) {
+    return *(volatile uint16_t*)reg;
+}
+
+static inline void mmio_write32(uintptr_t reg, uint32_t val) {
+    *(volatile uint32_t*)reg = val;
+}
+
+static inline uint32_t mmio_read32(uintptr_t reg) {
+    return *(volatile uint32_t*)reg;
+}
+
+static inline void mmio_write64(uintptr_t reg, uint64_t val) {
+    *(volatile uint64_t*)reg = val;
+}
+
+static inline uint64_t mmio_read64(uintptr_t reg) {
+    return *(volatile uint64_t*)reg;
+}
+
+// Memory barriers
+static inline void dsb(void) {
+    __asm__ volatile("dsb sy" ::: "memory");
+}
+
+static inline void dmb(void) {
+    __asm__ volatile("dmb sy" ::: "memory");
+}
+
+static inline void isb(void) {
+    __asm__ volatile("isb" ::: "memory");
+}
+
+// x86 I/O Port Emulation / Stubs for Portable Device Drivers
+static inline void outb(uint16_t port, uint8_t val) {
+    (void)port; (void)val;
+}
+
+static inline uint8_t inb(uint16_t port) {
+    (void)port;
+    return 0;
+}
+
+static inline void outw(uint16_t port, uint16_t val) {
+    (void)port; (void)val;
+}
+
+static inline uint16_t inw(uint16_t port) {
+    (void)port;
+    return 0;
+}
+
+static inline void outl(uint16_t port, uint32_t val) {
+    (void)port; (void)val;
+}
+
+static inline uint32_t inl(uint16_t port) {
+    (void)port;
+    return 0;
+}
+
+static inline void io_wait(void) {
+    __asm__ volatile("nop");
+}
+
+static inline void cli(void) {
+    __asm__ volatile("msr daifset, #2" ::: "memory");
+}
+
+static inline void sti(void) {
+    __asm__ volatile("msr daifclr, #2" ::: "memory");
+}
+
+static inline void hlt(void) {
+    __asm__ volatile("wfi");
+}
+
+#endif // _ARCH_AARCH64_IO_H

include/arch/aarch64/mmu.h

@@ -0,0 +1,39 @@
+#ifndef _ARCH_AARCH64_MMU_H
+#define _ARCH_AARCH64_MMU_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define MMU_PAGE_SIZE 4096
+
+// Memory Types / Attributes index for MAIR_EL1
+#define MT_DEVICE_nGnRnE 0
+#define MT_NORMAL_NC     1
+#define MT_NORMAL_WB     2
+
+#define MAIR_DEVICE_nGnRnE 0x00
+#define MAIR_NORMAL_NC     0x44
+#define MAIR_NORMAL_WB     0xFF
+
+#define MAIR_VAL ((MAIR_DEVICE_nGnRnE << (MT_DEVICE_nGnRnE * 8)) | \
+                  (MAIR_NORMAL_NC     << (MT_NORMAL_NC     * 8)) | \
+                  (MAIR_NORMAL_WB     << (MT_NORMAL_WB     * 8)))
+
+// Page descriptor bits
+#define PTE_VALID     (1ULL << 0)
+#define PTE_TABLE     (1ULL << 1)
+#define PTE_BLOCK     (0ULL << 1)
+#define PTE_USER      (1ULL << 6)
+#define PTE_RO        (1ULL << 7)
+#define PTE_SH_INNER  (3ULL << 8)
+#define PTE_AF        (1ULL << 10)
+#define PTE_NG        (1ULL << 11)
+#define PTE_PXN       (1ULL << 53)
+#define PTE_UXN       (1ULL << 54)
+
+#define PTE_ATTRINDX(x) (((uint64_t)(x)) << 2)
+
+void aarch64_mmu_init(void);
+void aarch64_mmu_map_2mb(uint64_t virt_addr, uint64_t phys_addr, uint32_t mem_type);
+
+#endif // _ARCH_AARCH64_MMU_H

include/arch/aarch64/timer.h

@@ -0,0 +1,13 @@
+#ifndef _ARCH_AARCH64_TIMER_H
+#define _ARCH_AARCH64_TIMER_H
+
+#include <stdint.h>
+
+#define ARCH_TIMER_VIRT_IRQ 27
+
+void     aarch64_timer_init(uint32_t freq_hz);
+uint64_t aarch64_timer_get_ticks(void);
+uint64_t aarch64_timer_get_freq(void);
+void     aarch64_timer_handle_irq(void);
+
+#endif // _ARCH_AARCH64_TIMER_H

include/arch/aarch64/uart.h

@@ -0,0 +1,34 @@
+#ifndef _ARCH_AARCH64_UART_H
+#define _ARCH_AARCH64_UART_H
+
+#include <stdint.h>
+#include <stddef.h>
+
+#define PL011_UART0_BASE 0x09000000
+
+// PL011 Registers
+#define UARTDR   0x000
+#define UARTRSR  0x004
+#define UARTFR   0x018
+#define UARTILPR 0x020
+#define UARTIBRD 0x024
+#define UARTFBRD 0x028
+#define UARTLCR  0x02C
+#define UARTCR   0x030
+#define UARTIFLS 0x034
+#define UARTIMSC 0x038
+#define UARTRIS  0x03C
+#define UARTMIS  0x040
+#define UARTICR  0x044
+
+// Flag register bits
+#define UARTFR_TXFF (1 << 5)
+#define UARTFR_RXFE (1 << 4)
+
+void uart_pl011_init(void);
+void uart_pl011_putc(char c);
+void uart_pl011_puts(const char* str);
+char uart_pl011_getc(void);
+int  uart_pl011_has_data(void);
+
+#endif // _ARCH_AARCH64_UART_H