feat(arch): Add armv8i (32-bit ARM/AArch32) architecture & complete TUI configurator

- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain
- Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC)
- Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU
- Support PL011 UART for early console & interactive LazyBox TTY input
- Update Makefile with make armv8i_defconfig and automated cross-compilation
- Update scripts/kconfig/menuconfig.py with dedicated armv8i options

include/arch/arch.h

@@ -79,7 +79,48 @@ static inline void arch_sleep(uint32_t ms) {
     }
 }
 
-// Prototype declarations for timer/interrupt compatibility
+uint64_t pit_get_ticks(void);
+void     pit_sleep(uint32_t ms);
+
+#elif defined(__arm__) || defined(__armv8i__)
+#define ARCH_NAME "armv8i"
+#define ARCH_IS_64BIT 0
+#include <arch/armv8i/arch.h>
+#include <arch/armv8i/cpu.h>
+#include <arch/armv8i/gic.h>
+#include <arch/armv8i/timer.h>
+#include <arch/armv8i/mmu.h>
+#include <arch/armv8i/uart.h>
+#include <arch/armv8i/io.h>
+
+static inline void arch_enable_interrupts(void) {
+    __asm__ volatile("cpsie i" ::: "memory");
+}
+
+static inline void arch_disable_interrupts(void) {
+    __asm__ volatile("cpsid i" ::: "memory");
+}
+
+static inline void arch_halt(void) {
+    __asm__ volatile("wfi");
+}
+
+static inline void arch_wait_for_interrupt(void) {
+    __asm__ volatile("cpsie i; wfi" ::: "memory");
+}
+
+static inline uint64_t arch_get_ticks(void) {
+    return armv8i_timer_get_ticks();
+}
+
+static inline void arch_sleep(uint32_t ms) {
+    uint64_t count = (ms > 10) ? (ms / 10) : 1;
+    uint64_t target = armv8i_timer_get_ticks() + count;
+    while (armv8i_timer_get_ticks() < target) {
+        __asm__ volatile("wfi");
+    }
+}
+
 uint64_t pit_get_ticks(void);
 void     pit_sleep(uint32_t ms);
 

include/arch/armv8i/arch.h

@@ -0,0 +1,23 @@
+#ifndef _ARCH_ARMV8I_ARCH_H
+#define _ARCH_ARMV8I_ARCH_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define ARMV8I_PAGE_SIZE 4096
+
+// Mode bits in CPSR
+#define CPSR_MODE_USR 0x10
+#define CPSR_MODE_FIQ 0x11
+#define CPSR_MODE_IRQ 0x12
+#define CPSR_MODE_SVC 0x13
+#define CPSR_MODE_MON 0x16
+#define CPSR_MODE_ABT 0x17
+#define CPSR_MODE_HYP 0x1A
+#define CPSR_MODE_UND 0x1B
+#define CPSR_MODE_SYS 0x1F
+
+#define CPSR_IRQ_DISABLE (1 << 7)
+#define CPSR_FIQ_DISABLE (1 << 6)
+
+#endif // _ARCH_ARMV8I_ARCH_H

include/arch/armv8i/cpu.h

@@ -0,0 +1,21 @@
+#ifndef _ARCH_ARMV8I_CPU_H
+#define _ARCH_ARMV8I_CPU_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+typedef struct {
+    uint32_t midr;
+    uint32_t mpidr;
+    uint32_t implementer;
+    uint32_t part_number;
+    uint32_t architecture;
+    char model_name[64];
+} armv8i_cpu_info_t;
+
+void armv8i_cpu_init(void);
+const armv8i_cpu_info_t* armv8i_get_cpu_info(void);
+uint32_t armv8i_get_midr(void);
+uint32_t armv8i_get_mpidr(void);
+
+#endif // _ARCH_ARMV8I_CPU_H

include/arch/armv8i/gic.h

@@ -0,0 +1,37 @@
+#ifndef _ARCH_ARMV8I_GIC_H
+#define _ARCH_ARMV8I_GIC_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#define GICD_BASE 0x08000000
+#define GICC_BASE 0x08010000
+
+// Distributor Registers
+#define GICD_CTLR            (GICD_BASE + 0x000)
+#define GICD_TYPER           (GICD_BASE + 0x004)
+#define GICD_IIDR            (GICD_BASE + 0x008)
+#define GICD_ISENABLER(n)    (GICD_BASE + 0x100 + ((n) * 4))
+#define GICD_ICENABLER(n)    (GICD_BASE + 0x180 + ((n) * 4))
+#define GICD_ISPENDR(n)      (GICD_BASE + 0x200 + ((n) * 4))
+#define GICD_ICPENDR(n)      (GICD_BASE + 0x280 + ((n) * 4))
+#define GICD_IPRIORITYR(n)   (GICD_BASE + 0x400 + ((n) * 4))
+#define GICD_ITARGETSR(n)    (GICD_BASE + 0x800 + ((n) * 4))
+#define GICD_ICFGR(n)        (GICD_BASE + 0xC00 + ((n) * 4))
+
+// CPU Interface Registers
+#define GICC_CTLR            (GICC_BASE + 0x000)
+#define GICC_PMR             (GICC_BASE + 0x004)
+#define GICC_BPR             (GICC_BASE + 0x008)
+#define GICC_IAR             (GICC_BASE + 0x00C)
+#define GICC_EOIR            (GICC_BASE + 0x010)
+
+typedef void (*gic_irq_handler_t)(uint32_t irq);
+
+void gic_init(void);
+void gic_enable_irq(uint32_t irq);
+void gic_disable_irq(uint32_t irq);
+void gic_set_priority(uint32_t irq, uint8_t prio);
+void gic_register_handler(uint32_t irq, gic_irq_handler_t handler);
+
+#endif // _ARCH_ARMV8I_GIC_H

include/arch/armv8i/io.h

@@ -0,0 +1,75 @@
+#ifndef _ARCH_ARMV8I_IO_H
+#define _ARCH_ARMV8I_IO_H
+
+#include <stdint.h>
+
+static inline void mmio_write8(uintptr_t reg, uint8_t val) {
+    *(volatile uint8_t*)reg = val;
+}
+
+static inline uint8_t mmio_read8(uintptr_t reg) {
+    return *(volatile uint8_t*)reg;
+}
+
+static inline void mmio_write16(uintptr_t reg, uint16_t val) {
+    *(volatile uint16_t*)reg = val;
+}
+
+static inline uint16_t mmio_read16(uintptr_t reg) {
+    return *(volatile uint16_t*)reg;
+}
+
+static inline void mmio_write32(uintptr_t reg, uint32_t val) {
+    *(volatile uint32_t*)reg = val;
+}
+
+static inline uint32_t mmio_read32(uintptr_t reg) {
+    return *(volatile uint32_t*)reg;
+}
+
+static inline void mmio_write64(uintptr_t reg, uint64_t val) {
+    *(volatile uint32_t*)reg = (uint32_t)(val & 0xFFFFFFFF);
+    *(volatile uint32_t*)(reg + 4) = (uint32_t)(val >> 32);
+}
+
+static inline uint64_t mmio_read64(uintptr_t reg) {
+    uint32_t low = *(volatile uint32_t*)reg;
+    uint32_t high = *(volatile uint32_t*)(reg + 4);
+    return ((uint64_t)high << 32) | low;
+}
+
+// Memory barriers
+static inline void dsb(void) {
+    __asm__ volatile("dsb" ::: "memory");
+}
+
+static inline void dmb(void) {
+    __asm__ volatile("dmb" ::: "memory");
+}
+
+static inline void isb(void) {
+    __asm__ volatile("isb" ::: "memory");
+}
+
+// x86 Port I/O Stubs
+static inline void outb(uint16_t port, uint8_t val) { (void)port; (void)val; }
+static inline uint8_t inb(uint16_t port) { (void)port; return 0; }
+static inline void outw(uint16_t port, uint16_t val) { (void)port; (void)val; }
+static inline uint16_t inw(uint16_t port) { (void)port; return 0; }
+static inline void outl(uint16_t port, uint32_t val) { (void)port; (void)val; }
+static inline uint32_t inl(uint16_t port) { (void)port; return 0; }
+static inline void io_wait(void) { __asm__ volatile("nop"); }
+
+static inline void cli(void) {
+    __asm__ volatile("cpsid i" ::: "memory");
+}
+
+static inline void sti(void) {
+    __asm__ volatile("cpsie i" ::: "memory");
+}
+
+static inline void hlt(void) {
+    __asm__ volatile("wfi");
+}
+
+#endif // _ARCH_ARMV8I_IO_H

include/arch/armv8i/mmu.h

@@ -0,0 +1,20 @@
+#ifndef _ARCH_ARMV8I_MMU_H
+#define _ARCH_ARMV8I_MMU_H
+
+#include <stdint.h>
+
+// VMSAv7 1MB Section Descriptor Flags
+#define SECTION_TYPE_MASK      (3 << 0)
+#define SECTION_TYPE_FAULT     (0 << 0)
+#define SECTION_TYPE_SECTION   (2 << 0)
+#define SECTION_BUFFERABLE     (1 << 2)
+#define SECTION_CACHEABLE      (1 << 3)
+#define SECTION_AP_RW_ALL      (3 << 10)
+#define SECTION_TEX_DEVICE     (0 << 12)
+#define SECTION_TEX_NORMAL     (1 << 12)
+#define SECTION_SHAREABLE      (1 << 16)
+#define SECTION_NON_GLOBAL     (1 << 17)
+
+void armv8i_mmu_init(void);
+
+#endif // _ARCH_ARMV8I_MMU_H

include/arch/armv8i/timer.h

@@ -0,0 +1,13 @@
+#ifndef _ARCH_ARMV8I_TIMER_H
+#define _ARCH_ARMV8I_TIMER_H
+
+#include <stdint.h>
+
+#define ARMV8I_TIMER_VIRT_IRQ 27
+
+void     armv8i_timer_init(uint32_t freq_hz);
+uint64_t armv8i_timer_get_ticks(void);
+uint64_t armv8i_timer_get_frequency(void);
+void     armv8i_timer_handle_irq(void);
+
+#endif // _ARCH_ARMV8I_TIMER_H

include/arch/armv8i/uart.h

@@ -0,0 +1,24 @@
+#ifndef _ARCH_ARMV8I_UART_H
+#define _ARCH_ARMV8I_UART_H
+
+#include <stdint.h>
+
+#define PL011_UART0_BASE 0x09000000
+
+#define UARTDR   0x000
+#define UARTRSR  0x004
+#define UARTFR   0x018
+#define UARTCR   0x030
+#define UARTIMSC 0x038
+#define UARTICR  0x044
+
+#define UARTFR_TXFF (1 << 5)
+#define UARTFR_RXFE (1 << 4)
+
+void uart_pl011_init(void);
+void uart_pl011_putc(char c);
+void uart_pl011_puts(const char* str);
+char uart_pl011_getc(void);
+int  uart_pl011_has_data(void);
+
+#endif // _ARCH_ARMV8I_UART_H