feat(arch): Add armv8i (32-bit ARM/AArch32) architecture & complete TUI configurator

- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain
- Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC)
- Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU
- Support PL011 UART for early console & interactive LazyBox TTY input
- Update Makefile with make armv8i_defconfig and automated cross-compilation
- Update scripts/kconfig/menuconfig.py with dedicated armv8i options

include/kernel/sync.h

@@ -15,15 +15,23 @@ static inline void spinlock_init(spinlock_t* lock) {
 }
 
 static inline void spin_lock(spinlock_t* lock) {
-    while (__atomic_test_and_set(&lock->lock, __ATOMIC_ACQUIRE)) {
 #if defined(__x86_64__)
+    while (__atomic_test_and_set(&lock->lock, __ATOMIC_ACQUIRE)) {
         __asm__ volatile ("pause");
-#elif defined(__aarch64__)
-        __asm__ volatile ("yield");
-#else
-        __asm__ volatile ("");
-#endif
     }
+#elif defined(__aarch64__)
+    while (__atomic_test_and_set(&lock->lock, __ATOMIC_ACQUIRE)) {
+        __asm__ volatile ("yield");
+    }
+#elif defined(__arm__) || defined(__armv8i__)
+    while (__atomic_test_and_set(&lock->lock, __ATOMIC_ACQUIRE)) {
+        __asm__ volatile ("nop");
+    }
+#else
+    while (__atomic_test_and_set(&lock->lock, __ATOMIC_ACQUIRE)) {
+        __asm__ volatile ("");
+    }
+#endif
 }
 
 static inline void spin_unlock(spinlock_t* lock) {