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subhobhai943andClaude Opus 4.8
0a874341c6
Kernel threads were only ever switched cooperatively (sched_yield, task_exit); a thread that never yielded held the CPU forever. The Weave scheduler now preempts from the PIT tick, so CPU-bound threads are time-sliced. Deferred switch, not mid-handler: - sched_tick() no longer switches. It charges the running quantum and, when it is spent, only raises weave_need_resched. The switch happens at IRQ return in the new sched_preempt_on_return(), called from the x86_64 dispatcher after the PIC EOI. That keeps the tick path re-entrancy-safe (the EOI is already out, so the PIC keeps delivering) and lets the preempted thread unwind through the normal iretq on its own kernel stack. Interrupt-atomic scheduler state: - The plain weave_lock is not IRQ-safe, so a tick landing mid-mutation would deadlock. weave_lock sections now mask interrupts (arch_irq_save/restore, added to arch.h for all three arches) so the timer can never fire inside them, and weave_rotate holds them masked across the pick and the register swap so the switch is one indivisible step. Preemption-disable count: - sched_preempt_disable/enable gate the tick and the return-path switch so a preemptive switch cannot land while a plain (non-IRQ-safe) spinlock is held. printk wraps its critical section with it, closing the most common hazard; other locks are a documented follow-up. Fresh threads opt into interrupts at entry so they are preemptible from birth without changing the cooperative early-boot self-test, which still runs with interrupts masked and is unchanged (20 switches, 3/3 workers). Verified on x86_64 under QEMU: a new boot-time self-test arms preemption and two threads that NEVER yield are forced to share the CPU -- 20 involuntary switches, both advance and are woven down to the CPU-bound lanes -- then boot proceeds cleanly to ring-3 /sbin/init and the shell with zero faults. aarch64 and armv8i still build; preemption is wired into the x86_64 IRQ path only, so those stay cooperative for now (their switch asm already exists). Co-Authored-By: Claude Opus 4.8 <[email protected]> Claude-Session: https://claude.ai/code/session_0161Jh7uCEMLYEMNPsjC1LKf
85 lines
5.0 KiB
Markdown
85 lines
5.0 KiB
Markdown
# SUB-OS Autonomous Development Roadmap
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This file is the cross-run memory for the continuous-development effort. Each
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run: read it, pick the single highest-value NEXT item achievable in one
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session, implement + verify it, then move it to DONE with a one-line result and
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refine the backlog.
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## Known-good build invocations (this host)
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- **Toolchain setup:** `apt-get install -y nasm gcc-aarch64-linux-gnu
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binutils-aarch64-linux-gnu gcc-arm-linux-gnueabihf binutils-arm-linux-gnueabihf
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qemu-system-x86 qemu-system-arm`; for Rust: `rustup target add x86_64-unknown-none`.
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- **x86_64:** `make x86_64_defconfig && make CROSS_COMPILE=x86_64-linux-gnu-
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CXX=x86_64-linux-gnu-g++ RUSTC="rustc --target x86_64-unknown-none"`
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- **aarch64:** `make aarch64_defconfig && make`
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- **armv8i:** `make armv8i_defconfig && make`
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- **Boot (x86_64, headless):** `qemu-system-x86_64 -drive format=raw,file=SUB-OS.img
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-m 256M -netdev user,id=net0 -device e1000,netdev=net0 -serial stdio -display none`
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(slow under TCG; the shell waits on input, so a timeout at the prompt is normal).
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## DONE
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- **Preemptive Weave scheduling from the timer tick** (2026-08-25):
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The PIT tick now drives involuntary context switches. sched_tick() only
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records that a quantum is spent (weave_need_resched); the switch happens at
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IRQ return in sched_preempt_on_return(), after the PIC EOI, on the
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interrupted thread's own kernel stack -- so the tick path stays re-entrancy
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safe and threads unwind cleanly through the normal iretq. The scheduler's
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lock sections were made interrupt-atomic (arch_irq_save/restore, new in
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arch.h) so the timer can never fire mid-mutation, and a preemption-disable
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count (sched_preempt_disable/enable, used by printk) keeps a switch from
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landing while a plain spinlock is held. Fresh preemptible kernel threads opt
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into interrupts at entry. Verified on x86_64 under QEMU: a boot-time self-test
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arms preemption and two NON-yielding worker threads are forced to share the
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CPU -- 20 involuntary switches, both workers advance and are woven down to the
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CPU-bound lanes -- then boot proceeds cleanly to ring-3 init and the shell
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with no faults. (Debugging note: an early re-entrancy guard deadlocked all
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preemption because sched_schedule() does not return to its caller until that
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thread is rescheduled; it was removed, since the masked switch already
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prevents nesting.)
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- **Weave scheduler + real kernel-thread context switching** (2026-08-25):
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Replaced the state-relabel-only round-robin with the SUB-OS "Weave" tiered
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scheduler backed by a genuine callee-saved context switch (`sub_ctx_switch`,
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per-arch assembly for x86_64/aarch64/armv8i) and a first-run trampoline.
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Threads run on their own kernel stacks; a task's lane floats on behaviour
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(voluntary yield → woven up, quantum-burn → woven down). Verified on x86_64
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under QEMU: a boot-time self-test runs 3 cooperative kernel threads to
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completion (20 real context switches, correct 1→2→3 round-robin interleave,
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clean return to the boot thread, then boot proceeds to ring-3 init + shell).
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ARM switch asm builds on both targets but is not yet boot-tested.
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## NEXT (prioritized backlog)
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1. **Thread reaping / zombie cleanup.** Exited kernel threads currently leak
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their 16 KB stack + task_t. Add a reaper (per-CPU dead list drained by the
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idle thread) so `task_exit` hands the corpse to it instead of leaking.
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2. **Boot-test the ARM context switch.** Wire a `weave_selftest()` call into the
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aarch64/armv8i boot paths and boot under `qemu-system-aarch64`/`-arm` to
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confirm the AArch64/AArch32 `sub_ctx_switch` frames are correct.
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3. **fork/exec/wait for the ring-3 userland.** Build on the existing ELF64
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loader + per-process page tables so `sh` can spawn and reap real children,
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not just the single builtin init.
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4. **An original capability-based IPC channel** ("sub-ports"): typed,
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capability-addressed message endpoints distinct from the SysV msg/pipe/shm
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set already present in `ipc/` — leaning into the "object-first" identity.
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5. **SMP bring-up (x86_64):** AP boot trampoline, per-CPU run lanes, and making
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the Weave lanes per-CPU with work-stealing between them.
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6. **GUI (feat/gui-desktop):** compositor damage tracking, a VFS-backed file
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manager, a text editor, and a settings panel over the toolkit widgets.
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## Notes / gotchas
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- `.S` files are run through cpp: no nested `/* ... */` comments.
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- `printk`/vsprintf supports only `c s d i u o x X p %` — no length modifiers
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(`l`, `ll`) and no field width; cast to `int`/`unsigned`/`void*`.
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- `list_del()` NULLs both links, so `list_empty()` is not a reliable "is this
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node queued?" test after a delete — check the links directly.
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- Preemption is armed after boot (step 14). A switch must NOT run while a plain
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spinlock is held: wrap such sections with sched_preempt_disable/enable (printk
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already does). weave_lock sections use arch_irq_save/restore so the tick
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cannot fire inside them.
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- During `subos_modular_core_boot()` step 13, hardware interrupts are still
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masked (enabled at step 14), so cooperative in-boot tests are deterministic.
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