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https://github.com/subhobhai943/SUB-OS.git
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subhobhai943andClaude Opus 4.8
0377726615
Add three real platform device drivers (x86 hardware, ARM-stubbed): - drivers/timer/hpet.c + include/drivers/hpet.h: High Precision Event Timer. Maps the HPET block at the standard 0xFED00000, reads the femtosecond period from the capability register, enables the main counter and exposes a monotonic nanosecond time source (hpet_get_ns) far finer than the 100 Hz PIT. - drivers/char/lpt.c + include/drivers/lpt.h: IBM PC parallel port (LPT1) with the Centronics data/strobe handshake over ports 0x378/0x379/0x37A. - drivers/char/nvram.c + include/drivers/nvram.h: MC146818 CMOS NVRAM read/write over 0x70/0x71, preserving the NMI-disable bit, with checksum and hex dump. Wired all three into the [5/14] device-enumeration boot step and added LazyBox applets `hpet`, `lpt`, and `nvram`. Verified live under QEMU (screenshotted): HPET reports 100 MHz / 3 comparators / 10 ns period and its counter advances ~1.4 s of real time between two `hpet` runs; NVRAM dumps 128 bytes with a computed checksum; LPT1 detected at 0x378. Clean build on x86_64/aarch64/armv8i; 0 panics / 0 OOM. Co-Authored-By: Claude Opus 4.8 <[email protected]> Claude-Session: https://claude.ai/code/session_01Fh5z6V7nGPbHvqVG5p4CXX
65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
// CMOS / RTC NVRAM driver for SUB-OS.
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//
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// Reads and writes the MC146818 CMOS register file behind ports 0x70/0x71.
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// The NMI-disable bit (0x80) of the index port is preserved on every access so
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// this driver never inadvertently re-enables NMIs.
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#include <drivers/nvram.h>
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#include <kernel/printk.h>
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#if defined(__x86_64__)
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#include <arch/x86_64/io.h>
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#define CMOS_INDEX 0x70
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#define CMOS_DATA 0x71
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#define CMOS_NMI_DISABLE 0x80
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uint8_t nvram_read(uint8_t index) {
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uint8_t prev = inb(CMOS_INDEX) & CMOS_NMI_DISABLE;
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outb(CMOS_INDEX, prev | (index & 0x7F));
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return inb(CMOS_DATA);
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}
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void nvram_write(uint8_t index, uint8_t value) {
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uint8_t prev = inb(CMOS_INDEX) & CMOS_NMI_DISABLE;
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outb(CMOS_INDEX, prev | (index & 0x7F));
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outb(CMOS_DATA, value);
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}
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uint8_t nvram_checksum(void) {
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uint16_t sum = 0;
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for (int i = NVRAM_USER_START; i < NVRAM_SIZE; i++) {
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sum += nvram_read((uint8_t)i);
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}
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return (uint8_t)(sum & 0xFF);
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}
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void nvram_dump(void) {
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printk(ANSI_BRIGHT_CYAN "CMOS NVRAM (128 bytes):\n" ANSI_RESET);
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for (int row = 0; row < NVRAM_SIZE; row += 16) {
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printk(" %02X: ", row);
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for (int col = 0; col < 16; col++) {
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printk("%02X ", nvram_read((uint8_t)(row + col)));
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}
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printk("\n");
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}
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}
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void nvram_init(void) {
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// Byte 0x0F is the BIOS shutdown status; reading it proves the port works.
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uint8_t shutdown_status = nvram_read(0x0F);
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printk(ANSI_BRIGHT_GREEN "NVRAM: " ANSI_RESET
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"CMOS scratch RAM ready (%d bytes, checksum 0x%02X, shutdown-status 0x%02X)\n",
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NVRAM_SIZE, nvram_checksum(), shutdown_status);
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}
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#else // CMOS/RTC NVRAM is an x86 platform device.
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uint8_t nvram_read(uint8_t index) { (void)index; return 0; }
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void nvram_write(uint8_t index, uint8_t v){ (void)index; (void)v; }
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uint8_t nvram_checksum(void) { return 0; }
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void nvram_dump(void) { }
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void nvram_init(void) { }
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#endif
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