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subhobhai943
7b646c8cc4
- Support ARMv8i / ARM32 (AArch32) baremetal target with arm-linux-gnueabihf toolchain - Implement ARMv8i boot entry point, banked exception mode stacks (IRQ, ABT, UND, SVC) - Implement 8 exception vectors, GICv2 distributor/CPU interface, CP15 Generic Timer (100 Hz), flat Section MMU - Support PL011 UART for early console & interactive LazyBox TTY input - Update Makefile with make armv8i_defconfig and automated cross-compilation - Update scripts/kconfig/menuconfig.py with dedicated armv8i options
63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
#include <arch/armv8i/gic.h>
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#include <arch/armv8i/io.h>
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#include <kernel/printk.h>
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void gic_init(void) {
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// 1. Disable Distributor and CPU interface during configuration
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mmio_write32(GICD_CTLR, 0);
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mmio_write32(GICC_CTLR, 0);
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// 2. Query lines count (TYPER ITLinesNumber)
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uint32_t typer = mmio_read32(GICD_TYPER);
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uint32_t lines = 32 * ((typer & 0x1F) + 1);
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// 3. Disable all interrupts & clear pending
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for (uint32_t i = 0; i < lines / 32; i++) {
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mmio_write32(GICD_ICENABLER(i), 0xFFFFFFFF);
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mmio_write32(GICD_ICPENDR(i), 0xFFFFFFFF);
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}
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// 4. Default priority 0xA0 and target CPU 0 (0x01)
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for (uint32_t i = 0; i < lines / 4; i++) {
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mmio_write32(GICD_IPRIORITYR(i), 0xA0A0A0A0);
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}
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for (uint32_t i = 8; i < lines / 4; i++) {
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mmio_write32(GICD_ITARGETSR(i), 0x01010101);
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}
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// 5. Enable Distributor (Group 0 & 1)
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mmio_write32(GICD_CTLR, 3);
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// 6. Set CPU Interface Priority Mask to allow all interrupts (0xF0)
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mmio_write32(GICC_PMR, 0xF0);
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// 7. Enable CPU Interface (Group 0 & 1)
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mmio_write32(GICC_CTLR, 3);
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// 8. Unmask Virtual Timer PPI 27
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gic_enable_irq(27);
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printk(KERN_INFO "GIC: ARM Generic Interrupt Controller v2 initialized (%u IRQ lines)\n", lines);
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}
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void gic_enable_irq(uint32_t irq) {
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uint32_t reg_idx = irq / 32;
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uint32_t bit_idx = irq % 32;
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mmio_write32(GICD_ISENABLER(reg_idx), (1 << bit_idx));
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}
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void gic_disable_irq(uint32_t irq) {
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uint32_t reg_idx = irq / 32;
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uint32_t bit_idx = irq % 32;
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mmio_write32(GICD_ICENABLER(reg_idx), (1 << bit_idx));
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}
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void gic_set_priority(uint32_t irq, uint8_t prio) {
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uint32_t reg_idx = irq / 4;
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uint32_t shift = (irq % 4) * 8;
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uint32_t val = mmio_read32(GICD_IPRIORITYR(reg_idx));
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val &= ~(0xFF << shift);
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val |= ((uint32_t)prio << shift);
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mmio_write32(GICD_IPRIORITYR(reg_idx), val);
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}
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